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PDF 82093AA Data sheet ( Hoja de datos )
| Número de pieza | 82093AA | |
| Descripción | I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC) | |
| Fabricantes | Intel Corporation | |
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PRELIMINARY
82093AA I/O ADVANCED
PROGRAMMABLE INTERRUPT
CONTROLLER (IOAPIC)
Provides Multiprocessor Interrupt
Management
Dynamic Interrupt Distribution-
Routing Interrupt to the Lowest
Priority Processor
Software Programmable Control of
Interrupt Inputs
Off Loads Interrupt Related Traffic
From the Memory Bus
24 Programmable Interrupts
13 ISA Interrupts Supported
4 PCI Interrupts
1 Interrupt/SMI# Rerouting
2 Motherboard Interrupts
1 Interrupt Used for INTR Input
3 General Purpose Interrupts
Independently Programmable for
Edge/Level Sensitivity Interrupts
Each Interrupt Can Be Programmed
to Respond to Active High or Low
Inputs
X-Bus Interface
CS For Flexible Decode of the
IOAPIC Device.
Index Register Interface for
Optimum Memory Usage
Registers are 32-Bit Wide to Match
the PCI to Host Bridge Architecture
Package 64-Pin PQFP
The 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides multi-processor interrupt
management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In
systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. Each interrupt pin is
individually programmable as either edge or level triggered. The interrupt vector and interrupt steering
information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space
needed to access the IOAPIC’s internal registers. To increase system flexibility when assigning memory space
usage, the The IOAPIC’s 2-register memory space is re-locatable.
D[7:0]
D/I#
A[1:0]
RD#
WR#
CS#
APCIREQ#
APICACK1#
A P I CA C K 2#
RESET
CLK
System
Bus
Interface
Clock
And
Reset
APIC
Bus
Interface
Interrupt
Controller
Test
APCID[1:0]
APCICLK
APCID[1:0]
APCICLK
APCICLK
TESTIN#
IOA_BLK
Figure 1. IOAPIC Simplified Block Diagram
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in
medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The
82093AA IOAPIC may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are
the property of their respective owners.
© INTEL CORPORATION 1996
May 1996
Order Number: 290566-001
1 page  
E
82093AA (IOAPIC)
2.0. SIGNAL DESCRIPTION
This section contains a detailed description of each signal. The signals are arranged in function groups
according to their interface.
Note that the “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the
high voltage level.
The terms' assertion and negation are used extensively. This is done to avoid confusion when working with a
mixture of ‘active-low’ and ‘active-high’ signals. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates
that a signal is inactive.
The following notations are used to describe the signal and type:
I
O
ST
OD
I/OD
I/O
Input pin
Output pin
Schmitt Trigger Input pin
Open Drain Output pin. This requires a pull-up to the VCC of the processor core
Bi-directional Input withOpen Drain Output pin.
Bi-directional Input/Output pin
2.1. System Bus Signals
Signal Name Type
Description
D[7:0]
I/O DATA: D[7:0] contain the data when writing to or reading from internal IOAPIC
registers. These signals are outputs when reading data from the IOAPIC and
they are inputs when writing data to the IOAPIC. These signals are tri-stated
during reset.
D/I# I DATA/INDEX#: This input selects whether the I/O Register Select
(IOREGSEL) Register or I/O Window (IOWIN) Register is accessed. All
internal IOAPIC registers are accessed with an indexing scheme. When the
D/I# pin is low, the IOREGSEL Register is accessed. When the D/I# pin is
high, the data becomes available from the register pointed to by the index
register. Typically, this signal is connected to SA4 on the ISA bus (i.e.,
IOREGSEL Register is at 00h and IOWIN Register is at 10h).
A[1:0]
I ADDRESS: The IOAPIC is a 32 bit device with an 8 bit ISA interface. A[1:0]
steer the data byte to the correct 8 bit location within the 32 bit register.
Typically, these input signals are connected to SA[1:0] of the ISA bus.
RD#
I READ STROBE: RD# causes the IOAPIC to respond by driving internal
register data onto the D[7:0] pins. Typically this pin is connected to the
MEMRD# signal on the ISA bus.
WR#
I WRITE STROBE: When this signal transitions from low to high, the data
present on the IOAPIC’s D[7:0] signals are written to an internal register.
Typically, this signal is connected to the MEMWR# signal on the ISA bus.
CS#
I CHIP SELECT: This active low input selects the IOAPIC as the target of the
current read or write transaction.
PRELIMINARY
5
5 Page 
E
82093AA (IOAPIC)
3.2.4. IOREDTBL[23:0]—I/O REDIRECTION TABLE REGISTERS
Address Offset:
Default Value:
Attribute:
10−11h (IOREDTBL0)
12−13h (IOREDTBL1)
14−15h (IOREDTBL2)
16−17h (IOREDTBL3)
18−19h (IOREDTBL4)
1A−1Bh (IOREDTBL5)
1C−1Dh (IOREDTBL6)
1E−1Fh (IOREDTBL7)
20−21h (IOREDTBL8)
22−23h (IOREDTBL9)
24−25h (IOREDTBL10)
26−27h (IOREDTBL11)
xxx1 xxxx xxxx xxxxh
Read/Write
28−29h (IOREDTBL12)
2A−2Bh (IOREDTBL13)
2C−2Dh (IOREDTBL14)
2E−2Fh (IOREDTBL15)
30−31h (IOREDTBL16)
32−33Fh (IOREDTBL17)
34−35h (IOREDTBL18)
36−37h (IOREDTBL19)
38−39h (IOREDTBL20)
3A−3Bh (IOREDTBL21)
3C−3Dh (IOREDTBL22)
3E−3Fh (IOREDTBL23)
There are 24 I/O Redirection Table entry registers. Each register is a dedicated entry for each interrupt input
signal. Unlike IRQ pins of the 8259A, the notion of interrupt priority is completely unrelated to the position of the
physical interrupt input signal on the APIC. Instead, software determines the vector (and therefore the priority)
for each corresponding interrupt input signal. For each interrupt signal, the operating system can also specify the
signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the
destination and delivery mode of the interrupt. The information in the redirection table is used to translate the
corresponding interrupt pin information into an inter-APIC message.
The IOAPIC responds to an edge triggered interrupt as long as the interrupt is wider than one CLK cycle. The
interrupt input is asynchronous; thus, setup and hold times need to be guaranteed for at lease one rising edge of
the CLK input. Once the interrupt is detected, a delivery status bit internal to the IOAPIC is set. A new edge on
that Interrupt input pin will not be recongnized until the IOAPIC Unit broadcasts the corresponding message over
the APIC bus and the message has been accepted by the destination(s) specified in the destination field. That
new edge only results in a new invocation of the handler if its acceptance by the destination APIC causes the
Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt wasn't already pending at the
destination.)
Bit
63:56
55:17
Description
Destination Field—R/W. If the Destination Mode of this entry is Physical Mode (bit 11=0), bits
[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field
potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical
destination address.
Destination Mode IOREDTBLx[11]
Logical Destination Address
0, Physical Mode
1, Logical Mode
IOREDTBLx[59:56] = APIC ID
IOREDTBLx[63:56] = Set of processors
Reserved.
PRELIMINARY
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