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PDF 80C58 Data sheet ( Hoja de datos )

Número de pieza 80C58
Descripción CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Fabricantes Advanced Analogic Technologies 
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No Preview Available ! 80C58 Hoja de datos, Descripción, Manual

8XC52 54 58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C52 80C52 80C32 87C54 80C54 87C58 80C58
See Table 1 for Proliferation Options
Y High Performance CHMOS EPROM
ROM CPU
Y 12 24 33 MHz Operations
Y Three 16-Bit Timer Counters
Y Programmable Clock Out
Y Up Down Timer Counter
Y Three Level Program Lock System
Y 8K 16K 32K On-Chip Program Memory
Y 256 Bytes of On-Chip Data RAM
Y Improved Quick Pulse Programming
Algorithm
Y Boolean Processor
Y 32 Programmable I O Lines
Y 6 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS 51 Microcontroller Compatible
Instruction Set
Y Power Saving Idle and Power Down
Modes
Y ONCE (On-Circuit Emulation) Mode
Y Four-Level Interrupt Priority
Y Extended Temperature Range Except
for 33 MHz Offering (b40 C to a85 C)
MEMORY ORGANIZATION
ROM
Device
EPROM
Version
ROMless
Version
ROM EPROM
Bytes
80C52
80C54
80C58
87C52
87C54
87C58
80C32
80C32
80C32
8K
16K
32K
These devices can address up to 64 Kbytes of external program data memory
RAM
Bytes
256
256
256
The Intel 8XC52 8XC54 8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s
reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC52 8XC54
8XC58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with
the existing MCS 51 family of products The 8XC52 8XC54 8XC58 is an enhanced version of the
87C51 80C51BH 80C31BH The added features make it an even more powerful microcontroller for applica-
tions that require clock output and up down counting capabilities such as motor control It also has a more
versatile serial channel that facilitates multi-processor communications
Throughout this document 8XC5X will refer to the 8XC52 80C32 8XC54 and 8XC58 unless information
applies to a specific device
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 272336-004

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80C58 pdf
8XC52 54 58
If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode
Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin
PSEN Program Store Enable is the read strobe to
external Program Memory
When the 8XC5X is executing code from external
Program Memory PSEN is activated twice each
machine cycle except that two PSEN activations
are skipped during each access to external Data
Memory
EA VPP External Access enable EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH Note however that if any of the
Lock bits are programmed EA will be internally
latched on reset
EA should be strapped to VCC for internal program
executions
This pin also receives the programming supply volt-
age (VPP) during EPROM programming
XTAL1 Input to the inverting oscillator amplifier
XTAL2 Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of a inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ‘‘Oscillators for Microcontrol-
lers’’ Order No 230659
272336 – 5
C1 C2 e 30 pF g10 pF for Crystals
For Ceramic Resonators contact resonator manufac-
turer
Figure 3 Oscillator Connections
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 floats as
shown in Figure 4 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the VIL
and VIH specifications the capacitance will not ex-
ceed 20 pF
272336 – 6
Figure 4 External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs
5

5 Page





80C58 arduino
8XC52 54 58
All other pins disconnected
TCLCH e TCHCL e 5 ns
272336 –9
Figure 7 ICC Test Condition Idle Mode
All other pins disconnected
272336 – 10
Figure 8 ICC Test Condition Power Down Mode
VCC e 2 0V to 6 0V
272336 – 11
Figure 9 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns
11

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