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PDF 80960SB Data sheet ( Hoja de datos )
| Número de pieza | 80960SB | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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80960SB
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
s High-Performance Embedded Architecture s Built-in Interrupt Controller
— 16 MIPS* Burst Execution at 16 MHz
— 4 Direct Interrupt Pins
— 5 MIPS Sustained Execution at 16 MHz — 31 Priority Levels, 256 Vectors
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
s Built-In Floating Point Unit
— Fully IEEE 754 Compatible
s Easy to Use, High Bandwidth 16-Bit Bus
— 25.6 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 32-Bit Address Space, 4 Gigabytes
s 80-Lead Quad Flat Pack (EIAJ QFP)
— 84-Lead Plastic Leaded Chip Carrier
(PLCC)
s Pin Compatible with 80960SA
s Software Compatible with
80960KA/KB/CA/CF Processors
The 80960SB is a member of Intel’s i960® 32-bit processor family, which is designed especially for low cost
embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in
interrupt controller. The 80960SB has a large register set, multiple parallel execution units and a 16-bit burst
bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess
of 5 million instructions per second*. The 80960SB is well-suited for a wide range of cost sensitive embedded
applications including non-impact printers, network adapters and I/O controllers.
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
ADDRESS
16-BIT
BURST
BUS
Figure 1. The 80960SB Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993
November 1993
Order Number: 272207-002
1 page  
80960SB
1.0 THE i960® PROCESSOR
The 80960SB is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
microprocessors were especially designed to serve
the needs of embedded applications. The embedded
market includes applications as diverse as industrial
automation, avionics, image processing, graphics
and networking. These types of applications require
high integration, low power consumption, quick
interrupt response times and high performance.
Since time to market is critical, embedded micropro-
cessors need to be easy to use in both hardware and
software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FETCH
INSTRUCTION
CACHE
LOAD
STORE
INSTRUCTION
STREAM
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
SIXTEEN 32-BIT
GLOBAL REGISTERS
g0
g15
SIXTEEN 32-BIT r0
LOCAL REGISTERS r15
FOUR 80-BIT
FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960SB Programming Environment
1
5 Page 
80960SB
1.1.9 Interrupt Handling
The 80960SB can be interrupted in one of two ways:
by the activation of one of four interrupt pins or by
sending a message on the processor’s data bus.
The 80960SB is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip
interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
1.1.10 Debug Features
The 80960SB has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers, the Process-Controls Word and the Trace-
Controls Word. By setting bits in these control words,
a software debug monitor can closely control how
the processor responds during program execution.
The 80960SB provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automati-
cally called.
The 80960SB also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960SB
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960SB’s
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.11 Fault Detection
The 80960SB has an automatic mechanism to
handle faults. Fault types include floating point, trace
and arithmetic faults. When the processor detects a
fault, it automatically calls the appropriate fault
handling routine and saves the current instruction
pointer and necessary state information to make
efficient recovery possible. Like interrupt handling
routines, fault handling routines are usually written to
meet the needs of specific applications and are often
included as part of the operating system or kernel.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. For example, a floating point fault may have the
subtype set to an Overflow or Zero-Divide fault. The
fault handler can use this specific information to
respond correctly to the fault.
1.1.12 Built-in Testability
Upon reset, the 80960SB automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960SB asserts its FAIL pin
and will not begin program execution. Self test takes
approximately 47,000 cycles to complete.
System manufacturers can use the 80960SB’s self-
test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.13 CHMOS
The 80960SB is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semicon-
ductor) process. The 80960SB is available at 10
MHz in the QFP package and at 10 and 16 MHz in
the PLCC package.
7
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