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PDF 80960KA Data sheet ( Hoja de datos )
| Número de pieza | 80960KA | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR | |
| Fabricantes | Intel Corporation | |
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80960KA
EMBEDDED 32-BIT MICROPROCESSOR
s High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-
tions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding
s 4 Gigabyte, Linear Address Space
s Pin Compatible with 80960KB
s Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large
register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,
this high performance processor is capable of execution rates in excess of 9.4 million instructions per second*.
The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and
specialty instrumentation.
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
Figure 1. The 80960KA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
May 1993
© INTEL CORPORATION, 1993
Order Number: 270775-005
1 page  
80960KA
1.1. Key Performance Features
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KA’s exceptional
performance:
1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the
80960KA provides thirty-two 32-bit registers. (See
Figure 2.)
2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most programs so
that execution speed can be improved by ensuring
that these core instructions are executed as quickly
as possible. The most frequently executed instruc-
tions such as register-register moves, add/subtract,
logical operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of times that
the processor must access memory to perform an
operation. As with other processors based on RISC
technology, the 80960KA has a Load/Store archi-
tecture. As such, only the LOAD and STORE instruc-
tions reference memory; all other instructions operate
on registers. This type of architecture simplifies
instruction decoding and is used in combination with
other techniques to increase parallelism.
4. Simple Instruction Formats. All instructions in
the 80960KA are 32 bits long and must be aligned on
word boundaries. This alignment makes it possible to
eliminate the instruction alignment stage in the
pipeline. To simplify the instruction decoder, there are
only five instruction formats; each instruction uses
only one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent instructions
to continue before the data has been returned from
memory, so that these instructions can overlap the
load. The 80960KA manages this process transpar-
ently to software through the use of a register score-
board. Conditional instructions also make use of a
scoreboard so that subsequent unrelated instructions
may be executed while the conditional instruction is
pending.
6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value is sent
immediately to its destination register. Yet at the same
time, the value is put on a bypass path to the ALU,
thereby saving the time that otherwise would be
required to retrieve the value for the next operation.
7. Bandwidth Optimizations. The 80960KA gets
optimal use of its memory bus bandwidth because the
bus is tuned for use with the on-chip instruction
cache: instruction cache line size matches the
maximum burst size for instruction fetches. The
80960KB automatically fetches four words in a burst
and stores them directly in the cache. Due to the size
of the cache and the fact that it is continually filled in
anticipation of needed instructions in the program
flow, the 80960KA is relatively insensitive to memory
wait states. The benefit is that the 80960KA delivers
outstanding performance even with a low cost
memory system.
8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then sends
it on to the instruction decoder at the same time it
updates the cache. Thus, no extra time is spent to
load and read the cache.
2
5 Page 
80960KA
Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLK2
I SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is divided
by two inside the 80960KA to generate the internal processor clock.
LAD31:0
I/O LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
T.S. from memory. During an address (Ta) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in words.
LAD1 LAD0
0 0 1 Word
0 1 2 Words
1 0 3 Words
1 1 4 Words
ALE O ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
T.S. asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active LOW and floats to a high impedance state during a hold cycle (Th).
ADS
O
O.D.
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta
state and deasserted during the following Td state. For a burst transaction, ADS is
asserted again every Td state where READY was asserted in the previous cycle.
W/R
O
O.D.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It
is latched on-chip and remains valid during Td cycles.
DT/R
O
O.D.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it is
high during Ta and Td cycles for a write. DT/R never changes state when DEN is
asserted.
READY
I READY indicates that data on LAD lines can be sampled or removed. If READY is not
asserted during a Td cycle, the Td cycle is extended to the next cycle by inserting a
wait state (Tw) and ADS is not asserted in the next cycle.
LOCK
I/O
O.D.
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. If the pin is
already asserted, the processor waits until it is not asserted. If the pin is not asserted,
the processor asserts LOCK during the Ta cycle of the read transaction. The
processor deasserts LOCK in the Ta cycle of the write transaction. During the time
LOCK is asserted, a bus agent can perform a normal read or write but not a RMW
operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to function
properly.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
8
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