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PDF 80960CF-33 Data sheet ( Hoja de datos )
| Número de pieza | 80960CF-33 | |
| Descripción | 80960CF-40/ -33/ -25/ -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR | |
| Fabricantes | Intel Corporation | |
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PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 71 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-Bit Burst Bus with Pipelining
s 32-Bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Manipulates 64-Bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
s Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
s On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
s On-Chip Instruction Cache
— 4 Kbyte Two-Way Set Associative
— 128-Bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
s High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
s Selectable Big or Little Endian Byte
Ordering
s Four On-Chip DMA Channels
— 71 Mbytes/s Fly-by Transfers
— 40 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
s 32-Bit Demultiplexed Burst Bus
— 128-Bit Internal Data Paths to and from
Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-Bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
s High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-Bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 625 ns Typical
s On-Chip Data Cache
— 1 Kbyte Direct-Mapped, Write Through
— 128 bits per Clock Access on Cache Hit
© INTEL CORPORATION, 1996
June 1996
Order Number: 272886-001
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CONTENTS
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Using External READY ............................................................................................................ 63
Terminating a Burst with BTERM ............................................................................................. 64
BOFF Functional Timing .......................................................................................................... 65
HOLD Functional Timing .......................................................................................................... 66
DREQ and DACK Functional Timing ....................................................................................... 67
EOP Functional Timing ............................................................................................................ 67
Terminal Count Functional Timing ........................................................................................... 68
FAIL Functional Timing ............................................................................................................ 68
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................. 69
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ......... 70
Idle Bus Operation ................................................................................................................... 71
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
80960CF Instruction Set ............................................................................................................ 4
80960CF Pin Description — External Bus Signals .................................................................... 6
80960CF Pin Description — Processor Control Signals ............................................................ 9
80960CF Pin Description — DMA and Interrupt Unit Control Signals ..................................... 11
80960CF PGA Pinout — In Signal Order ................................................................................ 14
80960CF PGA Pinout — In Pin Order ..................................................................................... 15
80960CF PQFP Pinout — In Signal Order (80960CF-33, -25, -16 Only) ................................ 17
80960CF PQFP Pinout — In Pin Order (80960CF-33, -25, -16 Only) ..................................... 18
Maximum TA at Various Airflows in oC (PGA Package Only) ................................................... 20
80960CF PGA Package Thermal Characteristics ................................................................... 21
80960CF PQFP Package Thermal Characteristics ................................................................. 21
Die Stepping Cross Reference ................................................................................................ 22
Operating Conditions ............................................................................................................... 23
DC Characteristics ................................................................................................................... 24
80960CF AC Characteristics (40 MHz) ................................................................................... 26
80960CF AC Characteristics (33 MHz) ................................................................................... 29
80960CF AC Characteristics (25 MHz) ................................................................................... 32
80960CF AC Characteristics (16 MHz) ................................................................................... 34
Reset Conditions ..................................................................................................................... 43
Hold Acknowledge and Backoff Conditions ............................................................................. 43
PRELIMINARY
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80960CF-40, -33, -25, -16
3.0 PACKAGE INFORMATION
3.1 Package Introduction
This section describes the pins, pinouts and thermal
characteristics for the 80960CF in the 168-pin
Ceramic Pin Grid Array (PGA) package; the
80960CF-33, -25, -16 devices are also available in
the 196-pin Plastic Quad Flat Package (PQFP). For
complete package specifications and information,
see the Packaging Handbook (# 240800).
3.2 Pin Descriptions
This section defines the 80960CF pins. Table 2
presents the legend for interpreting the pin descrip-
tions in the following tables. Pins associated with the
32-bit demultiplexed processor bus are described in
Table 2. Pins associated with the 80960CF DMA
Controller and Interrupt Unit are described in Table 3.
Pins associated with basic processor configuration
and control are described in Table 2.
All pins float while the processor is in the ONCE
mode.
Symbol
Description
I Input only pin
O Output only pin
I/O Pin can be either an input or output
– Pins “must be” connected as described
S(...)
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. Outputs are synchro-
nous to PCLK2:1.
S(E) Edge sensitive input
S(L) Level sensitive input
A(...)
Asynchronous. Inputs may be asynchro-
nous to PCLK2:1.
A(E) Edge sensitive input
A(L) Level sensitive input
H(...)
While the bus is in the Hold Acknowledge
or Bus Backoff state, the pin:
H(1)
H(0)
H(Z)
is driven to VCC
is driven to VSS
floats
H(Q) continues to be a valid input
R(...)
While the processor’s RESET pin is low,
the pin:
R(1)
R(0)
R(Z)
is driven to VCC
is driven to VSS
floats
R(Q) continues to be a valid output
PRELIMINARY
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