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PDF 8088 Data sheet ( Hoja de datos )

Número de pieza 8088
Descripción 8-BIT HMOS MICROPROCESSOR
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo

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1. Datasheet - 8-BIT HMOS Microprocessor






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8088
8-BIT HMOS MICROPROCESSOR
8088 8088-2
Y 8-Bit Data Bus Interface
Y 16-Bit Internal Architecture
Y Direct Addressing Capability to 1 Mbyte
of Memory
Y Direct Software Compatibility with 8086
CPU
Y 14-Word by 16-Bit Register Set with
Symmetrical Operations
Y 24 Operand Addressing Modes
Y Byte Word and Block Operations
Y 8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Y Two Clock Rates
5 MHz for 8088
8 MHz for 8088-2
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load silicon gate
technology (HMOS-II) and packaged in a 40-pin CERDIP package The processor has attributes of both 8-
and 16-bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and periph-
erals
231456 – 1
Figure 1 8088 CPU Functional Block Diagram
231456 – 2
Figure 2 8088 Pin Configuration
August 1990
Order Number 231456-006

1 page




8088 pdf
8088
Symbol
RQ GT0
RQ GT1
Pin No
30 31
LOCK
29
QS1 QS0 24 25
34
Type
IO
O
O
O
Table 1 Pin Description (Continued)
Name and Function
REQUEST GRANT pins are used by other local bus masters to force the
processor to release the local bus at the end of the processor’s current bus
cycle Each pin is bidirectional with RQ GT0 having higher priority than RQ
GT1 RQ GT has an internal pull-up resistor so may be left unconnected
The request grant sequence is as follows (See Figure 8)
1 A pulse of one CLK wide from another local bus master indicates a local
bus request (‘‘hold’’) to the 8088 (pulse 1)
2 During a T4 or TI clock cycle a pulse one clock wide from the 8088 to the
requesting master (pulse 2) indicates that the 8088 has allowed the local
bus to float and that it will enter the ‘‘hold acknowledge’’ state at the next
CLK The CPU’s bus interface unit is disconnected logically from the local
bus during ‘‘hold acknowledge’’ The same rules as for HOLD HOLDA apply
as for when the bus is released
3 A pulse one CLK wide from the requesting master indicates to the 8088
(pulse 3) that the ‘‘hold’’ request is about to end and that the 8088 can
reclaim the local bus at the next CLK The CPU then enters T4
Each master-master exchange of the local bus is a sequence of three
pulses There must be one idle CLK cycle after each bus exchange Pulses
are active LOW
If the request is made while the CPU is performing a memory cycle it will
release the local bus during T4 of the cycle when all the following conditions
are met
1 Request occurs on or before T2
2 Current cycle is not the low bit of a word
3 Current cycle is not the first acknowledge of an interrupt acknowledge
sequence
4 A locked instruction is not currently executing
If the local bus is idle when the request is made the two possible events will
follow
1 Local bus will be released during the next clock
2 A memory cycle will start within 3 clocks Now the four rules for a currently
active memory cycle apply with condition number 1 already satisfied
LOCK indicates that other system bus masters are not to gain control of the
system bus while LOCK is active (LOW) The LOCK signal is activated by
the ‘‘LOCK’’ prefix instruction and remains active until the completion of the
next instruction This signal is active LOW and floats to 3-state off in ‘‘hold
acknowledge’’
QUEUE STATUS provide status to allow external tracking of the internal
8088 instruction queue
The queue status is valid during the CLK cycle after which the queue
operation is performed
QS1
QS0
Characteristics
0(LOW)
0
1(HIGH)
1
0 No Operation
1 First Byte of Opcode from Queue
0 Empty the Queue
1 Subsequent Byte from Queue
Pin 34 is always high in the maximum mode
5

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8088 arduino
8088
ing the direction of the bus during read operations In
the event that a ‘‘NOT READY’’ indication is given
by the addressed device ‘‘wait’’ states (Tw) are in-
serted between T3 and T4 Each inserted ‘‘wait’’
state is of the same duration as a CLK cycle Periods
can occur between 8088 driven bus cycles These
are referred to as ‘‘idle’’ states (Ti) or inactive CLK
cycles The processor uses these cycles for internal
housekeeping
During T1 of any bus cycle the ALE (address latch
enable) signal is emitted (by either the processor or
the 8288 bus controller depending on the MN MX
strap) At the trailing edge of this pulse a valid ad-
dress and certain status information for the cycle
may be latched
Status bits S0 S1 and S2 are used by the bus con-
troller in maximum mode to identify the type of bus
transaction according to the following table
S2 S1 S0
Characteristics
0(LOW)
0
0
0
1(HIGH)
1
1
1
0
0
1
1
0
0
1
1
0 Interrupt Acknowledge
1 Read I O
0 Write I O
1 Halt
0 Instruction Fetch
1 Read Data from Memory
0 Write Data to Memory
1 Passive (No Bus Cycle)
Status bits S3 through S6 are multiplexed with high
order address bits and are therefore valid during T2
through T4 S3 and S4 indicate which segment reg-
ister was used for this bus cycle in forming the ad-
dress according to the following table
S4 S3
Characteristics
0(LOW) 0 Alternate Data (Extra Segment)
0 1 Stack
1(HIGH) 0 Code or None
1 1 Data
S5 is a reflection of the PSW interrupt enable bit S6
is always equal to 0
I O Addressing
In the 8088 I O operations can address up to a
maximum of 64K I O registers The I O address ap-
pears in the same format as the memory address on
bus lines A15–A0 The address lines A19–A16 are
zero in I O operations The variable I O instructions
which use register DX as a pointer have full address
capability while the direct I O instructions directly
address one or two of the 256 I O byte locations in
page 0 of the I O address space I O ports are ad-
dressed in the same manner as memory locations
Designers familiar with the 8085 or upgrading an
8085 design should note that the 8085 addresses
I O with an 8-bit address on both halves of the 16-
bit address bus The 8088 uses a full 16-bit address
on its lower 16 address lines
EXTERNAL INTERFACE
Processor Reset and Initialization
Processor initialization or start up is accomplished
with activation (HIGH) of the RESET pin The 8088
RESET is required to be HIGH for greater than four
clock cycles The 8088 will terminate operations on
the high-going edge of RESET and will remain dor-
mant as long as RESET is HIGH The low-going
transition of RESET triggers an internal reset se-
quence for approximately 7 clock cycles After this
interval the 8088 operates normally beginning with
the instruction in absolute locations FFFF0H (See
Figure 4) The RESET input is internally synchroniz-
ed to the processor clock At initialization the HIGH
to LOW transition of RESET must occur no sooner
than 50 ms after power up to allow complete initiali-
zation of the 8088
NMI asserted prior to the 2nd clock after the end of
RESET will not be honored If NMI is asserted after
that point and during the internal reset sequence
the processor may execute one instruction before
responding to the interrupt A hold request active
immediately after RESET will be honored before the
first instruction fetch
All 3-state outputs float to 3-state OFF during
RESET Status is active in the idle state for the first
clock after RESET becomes active and then floats
to 3-state OFF ALE and HLDA are driven low
Interrupt Operations
Interrupt operations fall into two classes software or
hardware initiated The software initiated interrupts
and software aspects of hardware interrupts are
specified in the instruction set description in the
iAPX 88 book or the iAPX 86 88 User’s Manual
Hardware interrupts can be classified as nonmaska-
ble or maskable
11

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