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PDF 80188 Data sheet ( Hoja de datos )
| Número de pieza | 80188 | |
| Descripción | HIGH-INTEGRATION 16-BIT MICROPROCESSORS | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Y Available in 10 MHz and 8 MHz
Versions
Y High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface 8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface 10 MHz (80186)
Y Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Y Numerics Coprocessing Capability
Through 8087 Interface
Y Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Y Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(b40 C to a85 C)
Figure 1 Block Diagram
272430 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
Order Number 272430-002
COPYRIGHT INTEL CORPORATION 1995
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80186 80188
Table 1 Pin Descriptions
Symbol
Pin
No Type
Name and Function
VCC 9 I SYSTEM POWER a5 volt power supply
43
VSS 26 I System Ground
60
RESET
57 O Reset Output indicates that the CPU is being reset and can be used as a system
reset It is active HIGH synchronized with the processor clock and lasts an
integer number of clock periods corresponding to the length of the RES signal
X1 59 I Crystal Inputs X1 and X2 provide external connections for a fundamental mode
X2 58 O parallel resonant crystal for the internal oscillator Instead of using a crystal an
external clock may be applied to X1 while minimizing stray capacitance on X2
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT)
CLKOUT
56 O Clock Output provides the system with a 50% duty cycle waveform All device
pin timings are specified relative to CLKOUT
RES
24 I An active RES causes the processor to immediately terminate its present
activity clear the internal logic and enter a dormant state This signal may be
asynchronous to the processor clock The processor begins fetching
instructions approximately 6 clock cycles after RES is returned HIGH For
proper initialization VCC must be within specifications and the clock signal must
be stable for more than 4 clocks with RES held LOW RES is internally
synchronized This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network
TEST
47 I O TEST is examined by the WAIT instruction If the TEST input is HIGH when
‘‘WAIT’’ execution begins instruction execution will suspend TEST will be
resampled until it goes LOW at which time execution will resume If interrupts
are enabled while the processor is waiting for TEST interrupts will be serviced
During power-up active RES is required to configure TEST as an input This pin
is synchronized internally
TMR IN 0
TMR IN 1
20 I Timer Inputs are used either as clock or control signals depending upon the
21 I programmed timer mode These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized
TMR OUT 0
TMR OUT 1
22 O Timer outputs are used to provide single pulse or continous waveform
23 O generation depending upon the timer mode selected
DRQ0
DRQ1
18 I DMA Request is asserted HIGH by an external device when it is ready for DMA
19 I Channel 0 or 1 to perform a transfer These signals are level-triggered and
internally synchronized
NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition
from LOW to HIGH is latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be asserted for at least one
clock The Non-Maskable Interrupt cannot be avoided by programming
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
45
44
42
41
I Maskable Interrupt Requests can be requested by activating one of these pins
I When configured as inputs these pins are active HIGH Interrupt Requests are
I O synchronized internally INT2 and INT3 may be configured to provide active-
I O LOW interrupt-acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure recognition all
interrupt requests must remain active until the interrupt is acknowledged When
Slave Mode is selected the function of these pins changes (see Interrupt
Controller section of this data sheet)
NOTE
Pin names in parentheses apply to the 80188
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80186 80188
The lower limit of memory defined by this chip select
is always 0H while the upper limit is programmable
By programming the upper limit the size of the
memory block is defined
MID-RANGE MEMORY CS
The processor provides four MCS lines which are
active within a user-locatable memory block This
block can be located within the 1-Mbyte memory ad-
dress space exclusive of the areas defined by UCS
and LCS Both the base address and size of this
memory block are programmable
PERIPHERAL CHIP SELECTS
The processor can generate chip selects for up to
seven peripheral devices These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address The base address
may be located in either memory or I O space Sev-
en CS lines called PCS0 –6 are generated by the
processor PCS5 and PCS6 can also be pro-
grammed to provide latched address bits A1 and A2
If so programmed they cannot be used as peripher-
al selects These outputs can be connected directly
to the A0 and A1 pins used for selecting internal
registers of 8-bit peripheral chips
READY GENERATION LOGIC
The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active In addition the proc-
essor may be programmed to either ignore external
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator
CHIP SELECT READY LOGIC AND RESET
Upon RESET the Chip-Select Ready Logic will per-
form the following actions
All chip-select outputs will be driven HIGH
Upon leaving RESET the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i e UMCS resets to FFFBH)
No other chip select or READY control registers
have any predefined values after RESET They
will not become active until the CPU accesses
their control registers Both the PACS and MPCS
registers must be accessed before the PCS lines
will become active
DMA Channels
The DMA controller provides two independent DMA
channels Data transfers can occur between memo-
ry and I O spaces (e g Memory to I O) or within the
same space (e g Memory to Memory or I O to I O)
Data can be transferred either in bytes or in words
(80186 only) to or from even or odd addresses
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers)
Each data transfer consumes 2 bus cycles (a mini-
mum of 8 clocks) one cycle to fetch data and the
other to store data This provides a maximum data
transfer rate of 1 25 Mword sec or 2 5 Mbytes sec
at 10 MHz (half of this rate for the 80188)
DMA CHANNELS AND RESET
Upon RESET the DMA channels will perform the
following actions
The Start Stop bit for each channel will be reset
to STOP
Any transfer in progress is aborted
Timers
The processor provides three internal 16-bit pro-
grammable timers Two of these are highly flexible
and are connected to four external pins (2 per timer)
They can be used to count external events time ex-
ternal events generate nonrepetitive waveforms
etc The third timer is not connected to any external
pins and is useful for real-time coding and time de-
lay applications In addition the third timer can be
used as a prescaler to the other two or as a DMA
request source
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