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PDF MAX159 Data sheet ( Hoja de datos )
| Número de pieza | MAX159 | |
| Descripción | +2.7V / Low-Power / 2-Channel / 108ksps / Serial 10-Bit ADCs in 8-Pin UMAX | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX159 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-1388; Rev 0; 11/98
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
General Description
The MAX157/MAX159 low-power, 10-bit analog-to-digi-
tal converters (ADCs) are available in 8-pin µMAX and
DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD = +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the 0.2µA automatic shutdown further
reduces power consumption.
The MAX157 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX159 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™ compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and a small package size, make
these converters ideal for battery-powered and data
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 12-bit upgrades, see the
MAX144/MAX145 data sheet.
Battery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process-Control Monitoring
Applications
Instrumentation
Test Equipment
Medical Instruments
System Supervision
Pin Configuration
TOP VIEW
VDD 1
CH0 (CH+) 2
CH1 (CH-) 3
GND 4
MAX157
MAX159
8 SCLK
7 DOUT
6 CS/SHDN
5 REF
µMAX/DIP
( ) ARE FOR MAX159 ONLY.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
o Single-Supply Operation (+2.7V to +5.25V)
o Two Single-Ended Channels (MAX157)
Single Pseudo-Differential Channel (MAX159)
o Low Power
0.9mA (at 108ksps, +3V)
100µA (at 10ksps, +3V)
10µA (at 1ksps, +3V)
<0.2µA (power-down mode)
o Internal Track/Hold
o 108ksps Sampling Rate
o SPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial Interface
o Space-Saving 8-Pin µMAX Package
o Pin-Compatible 12-Bit Upgrades Available
Ordering Information
PART
TEMP.
RANGE
PIN-
PACKAGE
MAX157ACUA 0°C to +70°C 8 µMAX
MAX157BCUA 0°C to +70°C 8 µMAX
MAX157ACPA 0°C to +70°C 8 Plastic DIP
MAX157BCPA 0°C to +70°C 8 Plastic DIP
MAX157AEUA -40°C to +85°C 8 µMAX
MAX157BEUA -40°C to +85°C 8 µMAX
MAX157AEPA -40°C to +85°C 8 Plastic DIP
MAX157BEPA -40°C to +85°C 8 Plastic DIP
MAX157AMJA -55°C to +125°C 8 CERDIP*
MAX157BMJA -55°C to +125°C 8 CERDIP*
MAX159ACUA 0°C to +70°C 8 µMAX
MAX159BCUA 0°C to +70°C 8 µMAX
MAX159ACPA 0°C to +70°C 8 Plastic DIP
MAX159BCPA 0°C to +70°C 8 Plastic DIP
MAX159AEUA -40°C to +85°C 8 µMAX
MAX159BEUA -40°C to +85°C 8 µMAX
MAX159AEPA -40°C to +85°C 8 Plastic DIP
MAX159BEPA -40°C to +85°C 8 Plastic DIP
MAX159AMJA -55°C to +125°C 8 CERDIP*
MAX159BMJA -55°C to +125°C 8 CERDIP*
*Contact factory for availability.
INL
(LSB)
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1500
VREF = VDD
RL = ∞
1300 CL = 50pF
CODE = 1010101000
1100
900
SUPPLY CURRENT
vs. TEMPERATURE
1500
VREF = VDD
RL = ∞
1250
CL = 50pF
CODE = 1010101000
1000
10,000
1000
SUPPLY CURRENT
vs. SAMPLING RATE
VREF = VDD
CODE = 1010101000
CL = 50pF
100
10
750
700
1
500
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
500
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
0.1
0.1 1
10 100 1k 10k 100k
SAMPLING RATE (sps)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
1000
VREF = VDD
800
SHUTDOWN CURRENT
vs. TEMPERATURE
1000
VREF = VDD
800
600 600
400 400
200 200
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
OFFSET ERROR vs. SUPPLY VOLTAGE
0.20
0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
0.20
0.15 0.15
0.10 0.10
0.05 0.05
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
0
-60 -35 -10 15 40 65 90 115 140
TEMPERATURE (°C)
_______________________________________________________________________________________ 5
5 Page 
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE
DOUT (Internal Clock)
DOUT (External Clock)
1
EOC
1
2
1
1
3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 CHID D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
1 CHID D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise (which includes all
spectral components minus the fundamental), the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
Signal-to-noise plus distortion is the ratio of the funda-
mental input frequency’s RMS amplitude to RMS equiv-
alent of all other ADC output signals:
⋅SINAD(dB) = 20
log
SignalRMS
(Noise + Distortion)RMS
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the effective number of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
⋅ ( )THD = 20
log
V22 + V32 + V42 + V52
V12
where V1 is the fundamental amplitude and V2 through
V5 are the amplitudes of the 2nd through 5th-order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX157/MAX159 interface is fully compatible with
SPI/QSPI and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX157/MAX159. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (tWAKE) speci-
fied before activating SCLK.
3) Activate SCLK for a minimum of 16 clock cycles. The
first falling clock edge will generate a serial data-
stream of three leading ones, followed by the chan-
nel identification, the MSB of the digitized input
signal, and two sub-bits. DOUT transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing char-
acteristic. Data should be clocked into the µP on
SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the sub-bits.
5) With CS/SHDN high, wait at least 60ns (tCS), before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output either in two 8-bit sequences or
continuously. The bytes will contain the result of the
conversion padded with three leading ones, the chan-
nel identification before the MSB, and two trailing sub-
bits. If the serial clock hasn’t been idled after the last
sub-bit (S0) and CS/SHDN is kept low, DOUT sends
trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c). Two
consecutive 8-bit readings are necessary to obtain the
entire 10-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
µP on SCLK’s rising edge. The first 8-bit data stream
contains three leading ones, followed by channel identi-
fication and the first four data bits starting with the MSB.
The second 8-bit data stream contains the remaining
bits, D5 through D0, and the sub-bits S1 and S0.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX159.PDF ] | |
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