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PDF MAX1492 Data sheet ( Hoja de datos )
| Número de pieza | MAX1492 | |
| Descripción | Single-Chip ADCs | |
| Fabricantes | Maxim Integrated | |
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19-2959; Rev 4; 7/10
EVAALVUAAILTAIOBNLEKIT
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
General Description
The MAX1492/MAX1494 low-power, 3.5- and 4.5-digit,
analog-to-digital converters (ADCs) with integrated liquid
crystal display (LCD) drivers operate from a single 2.7V
to 5.25V power supply. They include an internal refer-
ence, a high-accuracy on-chip oscillator, and a triplexed
LCD driver. An internal charge pump generates the neg-
ative supply needed to power the integrated input buffer
for single-supply operation. The ADCs are configurable
for either a ±2V or ±200mV input range and outputs its
conversion results to an LCD and/or to a microcontroller
(µC). µC communication is facilitated through an
SPI™-/QSPI™-/MICROWIRE®-compatible serial inter-
face. The MAX1492 is a 3.5-digit (±1999 count) device,
and the MAX1494 is a 4.5-digit (±19,999 count) device.
The MAX1492/MAX1494 do not require external-preci-
sion integrating capacitors, autozero capacitors, crystal
oscillators, charge pumps, or other circuitry required
with dual-slope ADCs (commonly used in panel meter
circuits).
These devices also feature on-chip buffers for the dif-
ferential signal and reference inputs, allowing direct
interface with high-impedance signal sources. In addi-
tion, they use continuous internal-offset calibration and
offer >100dB simultaneous rejection of 50Hz and 60Hz
line noise. Other features include data hold and peak
hold, overrange and underrange detection, and a low-
battery monitor.
The MAX1494 comes in a 32-pin, 7mm x 7mm LQFP
package, and the MAX1492 comes in 28-pin SSOP and
28-pin PDIP packages. All devices in this family operate
over the 0°C to +70°C commercial temperature range.
Digital Panel Meters
Hand-Held Meters
Digital Voltmeters
Digital Multimeters
Applications
Features
o High Resolution
MAX1494: 4.5 Digits (±19,999 Count)
MAX1492: 3.5 Digits (±1999 Count)
o Sigma-Delta ADC Architecture
No Integrating Capacitors Required
No Autozeroing Capacitors Required
>100dB of Simultaneous 50Hz and 60Hz
Rejection
o Operate from a Single 2.7V or 5.25V Supply
o Selectable Input Range of ±200mV or ±2V
o Selectable Voltage Reference: Internal 2.048V
or External
o Internal High-Accuracy Oscillator Needs No
External Components
o Automatic Offset Calibration
o Low Power
Maximum 960µA Operating Current
Maximum 400µA Shutdown Current
o Small 32-Pin 7mm x 7mm LQFP Package
(4.5 Digits), 28-Pin SSOP Package (3.5 Digits)
o Triplexed LCD Driver
o SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
o Evaluation Kit Available (Order MAX1494EVKIT)
Ordering Information/
Selector Guide
PART
TEMP
RANGE
PIN-
RESOLUTION
PACKAGE (DIGITS)
MAX1492CAI+ 0°C to +70°C 28 SSOP
3.5
MAX1492CNI+ 0°C to +70°C 28 PDIP
3.5
MAX1494CCJ+ 0°C to +70°C 32 LQFP
4.5
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
TIMING CHARACTERISTICS (Notes 10, 11 and Figure 13)
(VAVDD = VDVDD = 2.7V to 5.25V, VGND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
fSCLK
tCH
tCL
tDS
tDH
tCSS
tCSH
tDO
tTR
tDV
CLOAD = 50pF (Figures 18, 19)
CLOAD = 50pF (Figures 18, 19)
CLOAD = 50pF (Figures 18, 19)
0 4.2 MHz
100 ns
100 ns
50 ns
0 ns
50 ns
0 ns
120 ns
120 ns
120 ns
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Note 2: Offset calibrated. See the OFFSET_CAL1 and OFFSET_CAL2 sections in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8: CLK and SCLK are idle.
Note 9: Power-supply currents are measured with all digital inputs at either GND or DVDD and with the device in internal clock mode.
Note 10: All input signals are specified with tRISE = tFALL = 5ns (10% to 90% of DVDD) and are timed from a voltage level of 50% of
DVDD, unless otherwise noted.
Note 11: See the serial-interface timing diagrams.
_______________________________________________________________________________________ 5
5 Page 
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
ten times the first-notch frequency and 60Hz is equal to
12 times the first-notch frequency.
For large step changes at the input, allow a settling
time of 800ms before valid data is read.
XYZ
Clock Modes
Configure the MAX1492/MAX1494 to use either the
internal oscillator or an externally applied clock to drive
the modulator and filter. Set the EXTCLK bit in the con-
trol register to 0 to put the device in internal clock mode.
Set the EXTCLK bit high to put the device in external
clock mode. Connect CLK to GND or DVDD when using
the internal oscillator. The MAX1492/MAX1494 ideally
operate with a 4.9152MHz clock to achieve maximum
rejection of 50Hz/60Hz common-mode, power-supply,
and normal-mode noise.
Internal Clock Mode
The MAX1492/MAX1494 contain an internal oscillator.
The power-up condition for the MAX1492/MAX1494 is
internal clock operation with the EXTCLK bit in the con-
trol register equal to 0. Using the internal oscillator
saves board space by removing the need for an exter-
nal clock source.
External Clock Mode
For external clock operation, set the EXTCLK bit in the
control register high and drive CLK with a 4.9152MHz
clock source. Using an external clock allows for custom
conversion rates. A 2.4576MHz clock signal reduces
the conversion rate and the LCD update rate by a fac-
tor of two. The MAX1492/MAX1494 operate with an
external clock source of up to 5.05MHz.
Charge Pump
The MAX1492/MAX1494 contain an internal charge
pump to provide the negative supply voltage for the inter-
nal analog input/reference buffers. The bipolar input
range of the analog input/reference buffers allows this
device to accept negative inputs with high source imped-
ances. Connect a 0.1µF capacitor from VNEG to GND.
LCD Driver
The MAX1492/MAX1494 contain the necessary back-
plane and segment-driver outputs to drive 3.5-digit
a
f
b
a
BP1 f b
gg
e
d
DP
c BP2
ANNUNCIATOR
BP3
DP
e
d
c
ANNUNCIATOR
Figure 3. Connection Diagrams for Typical 7-Segment Displays
(MAX1492) and 4.5-digit (MAX1494) LCDs. The LCD
update rate is 2.5Hz. Figures 4–7 show the connection
schemes for a standard LCD. The MAX1492/MAX1494
automatically display the results of the ADC, if desired.
The MAX1492/MAX1494 also allow independent control
of the LCD driver through the serial interface, allowing
for data processing of the ADC result before showing
the result on the LCD. Additionally, each LCD segment
can be individually controlled (see the LCD Segment-
Display Register sections).
Triplexing
An internal resistor string comprised of three equal-
value resistors (52kΩ, 1% matching) is used to gener-
ate the display drive voltages. On the MAX1492, one
end of the string is connected to DVDD and the other
end is connected to GND. On the MAX1494, the other
end of the resistor string is connected to VDISP. Note
that VLCD should be three times the threshold voltage
for the liquid crystal material used (Figure 9).
The connection diagrams for a typical 7-segment dis-
play-font decimal point and annunciators are illustrated
in Figures 3 and 8. The MAX1494/MAX1492 numeric
display drivers (4.5 digits, 3.5 digits) use this configura-
tion to drive a triplexed LCD with three backplanes and
13 segment-driver lines (10 for 3.5 digits). Figures 4
Table 1. List of Custom LCD Manufacturers
MANUFACTURER
WEBSITE
PART NUMBER
04-0924-00
DCI, Inc.
www.dciincorporated.com
04-0924-01
04-0925-00
04-0925-01
The following site has links to other custom LCD manufacturers: www.earthlcd.com/mfr.htm
DESCRIPTION
3.5 digits, 5V
3.5 digits, 3V
4.5 digits, 5V
4.5 digits, 3V
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX1492.PDF ] | |
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