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PDF MAX1458 Data sheet ( Hoja de datos )

Número de pieza MAX1458
Descripción 1%-Accurate / Digitally Trimmed Sensor Signal Conditioner
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX1458 Hoja de datos, Descripción, Manual

19-1373; Rev 0; 5/98
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
General Description
The MAX1458 highly integrated analog-sensor signal
processor is optimized for piezoresistive sensor calibra-
tion and compensation without any external compo-
nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit
DACs. Achieving a total error factor within 1% of the
sensor’s repeatability errors, the MAX1458 compen-
sates offset, offset temperature coefficient, full-span
output (FSO), FSO temperature coefficient (FSOTC),
and FSO nonlinearity of silicon piezoresistive sensors.
The MAX1458 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via digital-to-analog converters (DACs),
thereby eliminating quantization noise. Built-in testabili-
ty features on the MAX1458 result in the integration of
three traditional sensor-manufacturing operations into
one automated process:
Pretest: Data acquisition of sensor performance
under the control of a host test computer.
Calibration and compensation: Computation and
storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1458.
Final test operation: Verification of transducer cali-
bration and compensation without removal from the
pretest socket.
Although optimized for use with piezoresistive sensors,
the MAX1458 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.
______________________Customization
Maxim can customize the MAX1458 for unique require-
ments. With a dedicated cell library consisting of more
than 90 sensor-specific functional blocks, Maxim can
quickly provide customized MAX1458 solutions. Please
contact Maxim for further information.
________________________Applications
Piezoresistive Pressure and Acceleration
Transducers and Transmitters
MAP (Manifold Absolute Pressure) Sensors
Automotive Systems
Hydraulic Systems
Industrial Pressure Sensors
Features
o Medium Accuracy (±1%), Single-Chip Sensor
Signal Conditioning
o Sensor Errors Trimmed Using Correction
Coefficients Stored in Internal EEPROM—
Eliminates the Need for Laser Trimming and
Potentiometers
o Compensates Offset, Offset-TC, FSO, FSOTC,
FSO Linearity
o Programmable Current Source (0.1mA to 2.0mA)
for Sensor Excitation
o Fast Signal-Path Settling Time (<1ms)
o Accepts Sensor Outputs from 10mV/V to 40mV/V
o Fully Analog Signal Path
Ordering Information
PART
TEMP. RANGE PIN-PACKAGE
MAX1458CAE
0°C to +70°C
16 SSOP
MAX1458C/D
0°C to +70°C
Dice*
MAX1458AAE
-40°C to +125°C 16 SSOP
*Dice are tested at TA = +25°C, DC parameters only.
Functional Diagram appears at end of data sheet.
Pin Configuration
TOP VIEW
SCLK 1
CS 2
I.C. 3
TEMP 4
FSOTC 5
DIO 6
WE 7
VSS 8
MAX1458
SSOP
16 LIMIT
15 VDD
14 INP
13 BDRIVE
12 INM
11 I.C.
10 OUT
9 ISRC
________________________________________________________________ Maxim Integrated Products 1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.

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MAX1458 pdf
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
FSOTC Compensation
Silicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(VBDRIVE) increases with temperature. This depen-
dence of VBDRIVE on the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi-
tivity tempco (TCS) so that, with constant voltage exci-
tation, full-span output (FSO) will decrease with
temperature, causing a full-span output temperature
coefficient (FSOTC) error. However, if the bridge volt-
age can be made to increase with temperature at the
same rate that TCS decreases with temperature, the
FSO will remain constant.
FSOTC compensation is accomplished by resistor
RFTC and the FSOTC DAC, which modulate the excita-
tion reference current at ISRC as a function of tempera-
ture (Figure 3). FSO DAC sets VISRC and remains
constant with temperature while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
VBDRIVE, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSOTC errors are
compensated and FSO will be constant with tempera-
ture.
OFFSET TC Compensation
Compensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
VBDRIVE that must be added to the output summing
junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).
Analog Signal Path
The fully differential analog signal path consists of four
stages:
Front-end summing junction for coarse offset correction
3-bit PGA with eight selectable gains ranging from
41 through 230
Three-input-channel summing junction
Differential to single-ended output buffer (Figure 2)
Coarse Offset Correction
The sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR > 90dB, an input impedance of approxi-
mately 1M, and a common-mode input voltage range
from VSS to VDD. At this summing junction, a coarse off-
set-correction voltage is added, and the resultant volt-
age is fed into the PGA. The 3-bit (plus sign)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage ref-
erence is 1.25% of VDD; thus, a VDD of 5V results in a
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).
4.5
FULL-SPAN OUTPUT (FSO)
0.5
OFFSET
PMIN
FULL-SCALE (FS)
PMAX
PRESSURE
1.25% VDD
IRO
DAC
INP
INM
BDRIVE
OFFTC
DAC
SOTC
A2 A1 A0
A = 2.3
± LIMIT
Σ PGA
Σ OUT
A=1
A = 2.3
VDD
Offset
DAC
±
SOFF
Figure 1. Typical Pressure-Sensor Output
Figure 2. Signal-Path Block Diagram
_______________________________________________________________________________________ 5

5 Page





MAX1458 arduino
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
high. In addition, the EEPROM should only be written to
at TA = +25°C and VDD = 5V.
Writing to the internal EEPROM is a time-consuming
process and should only be required once. All calibra-
tion/compensation coefficients are determined by writ-
ing directly to the DAC and configuration registers. Use
the following procedure to write these calibration/com-
pensation coefficients to the EEPROM:
1) Issue an ERASE EEPROM command.
2) Wait 50ms (tWRITE).
3) Issue on END EEPROM WRITE command at
address 00h.
4) Wait 1ms (tWAIT).
5) Issue a BEGIN EEPROM WRITE command
(Figure 7) at the address of the bit to be set.
6) Wait 50ms.
7) Issue an END EEPROM WRITE command (Figure 7)
using the same address as in Step 5.
8) Wait 1ms.
9) Return to Step 5 until all necessary bits have been
set.
10) Read EEPROM to verify that the correct calibra-
tion/compensation coefficients have been stored.
READ EEPROM Command
The READ EEPROM command returns the bit stored at
the memory location addressed by the lower seven bits
of the data field (A0–A6). The higher bits of the data
field (A7–A11) are ignored. Note that after a read com-
mand has been issued, the DIO lines become an out-
put and the state of the addressed EEPROM location
will be available on DIO 200µs (tREAD) after the falling
edge of the 16th SCLK cycle (Figure 8). After issuing
the READ EEPROM command, DIO returns to input
mode on the falling edge of CS. Reading the entire
EEPROM requires the READ EEPROM command be
issued 128 times.
SCLK
DIO
SCLK
DATA
COMMAND
LSB
MSB LSB
MSB
A0 A1 A2 A3 A4 A5 A6 0 0 0 0 0 0 1 0 0
16-BIT COMMAND WORD – BEGIN EEPROM WRITE AT ADDRESS COMMAND
LSB
MSB
DATA
COMMAND
LSB
MSB LSB
MSB
DIO A0 A1 A2 A3 A4 A5 A6 0 0 0 0 0 1 0 1 0
16-BIT COMMAND WORD – END EEPROM WRITE AT ADDRESS COMMAND
LSB MSB
Figure 7. Begin WRITE EEPROM and End WRITE EEPROM Timing Diagrams
CS
tMIN = 200µs
16 CLOCK CYCLES
SCLK
tREAD
DIO X 1 0 1 0 U 0 A0 A1 A2 A3 A4 A5 A6 0 0 0 0 0 1 1 0 0 X EE DATA
INIT SEQUENCE
READ EEPROM AT ADDRESS COMMAND
DIO IS AN INPUT PIN
DIO IS AN
OUTPUT PIN
Figure 8. READ EEPROM Timing Diagram
X
______________________________________________________________________________________ 11

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