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PDF MAX1449 Data sheet ( Hoja de datos )
| Número de pieza | MAX1449 | |
| Descripción | 10-Bit / 105Msps / Single +3.3V / Low-Power ADC with Internal Reference | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1449 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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19-4802; Rev 0; 10/00
EVALUATION KIT AVAILABLE
10-Bit, 105Msps, Single +3.3V, Low-Power
ADC with Internal Reference
General Description
The MAX1449 +3.3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10-
stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully
differential signal path. The ADC is optimized for low-
power, high-dynamic performance in imaging and digi-
tal communications applications. The converter
operates from a single +2.7V to +3.6V supply, consum-
ing only 186mW while delivering a 58.5dB (typ) signal-
to-noise ratio (SNR) at a 20MHz input frequency. The
fully differential input stage has a -3dB 400MHz band-
width and may be operated with single-ended inputs. In
addition to low operating power, the MAX1449 features
a 5µA power-down mode for idle periods.
An internal +2.048V precision bandgap reference is
used to set the ADC’s full-scale range. A flexible refer-
ence structure allow’s the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Lower speed, pin-compatible versions of the MAX1449
are also available. Refer to the MAX1444 data sheet for
a 40Msps version, the MAX1446 data sheet for a
60Msps version, and the MAX1448 data sheet for 80Msps.
The MAX1449 has parallel, offset binary, CMOS-com-
patible, three-state outputs that can be operated from
+1.7V to +3.6V to allow flexible interfacing. The device
is available in a 5mm x 5mm 32-pin TQFP package and
is specified over the extended industrial (-40°C to
+85°C) temperature range.
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
Pin Configuration appears at end of data sheet.
Features
o Single +3.3V Operation
o Excellent Dynamic Performance
58.5dB SNR at fIN = 20MHz
72dBc SFDR at fIN = 20MHz
o Low Power
62mA (Normal Operation)
5µA (Shutdown Mode)
o Fully Differential Analog Input
o Wide 2Vp-p Differential Input Voltage Range
o 400MHz -3dB Input Bandwidth
o On-Chip +2.048V Precision Bandgap Reference
o CMOS-Compatible Three-State Outputs
o 32-Pin TQFP Package
o Evaluation Kit Available
PART
MAX1449EHJ
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Pin-Compatible, Lower Speed
Selection Table
PART NUMBER
MAX1444
MAX1446
MAX1448
SAMPLING SPEED
40Msps
60Msps
80Msps
Functional Diagram
CLK
IN+
T/H
IN-
PD REF
CONTROL
PIPELINE ADC
REF SYSTEM +
BIAS
MAX1449
VDD
GND
D
E
C
10
OUTPUT
DRIVERS
D9–D0
OVDD
OGND
REFOUT REFIN REFP COM REFN
OE
________________________________________________________________ Maxim Integrated Products 1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
10-Bit, 105Msps, Single +3.3V, Low-Power
ADC with Internal Reference
Typical Operating Characteristics
(VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C,
unless otherwise noted.)
FFT PLOT (fIN = 7.5MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
0
SNR = 58.6dB
-10 SINAD = 58.4dB
-20 THD = -72.7dBc
SFDR = 73.6dBc
-30
-40
-50 2ND HARMONIC
-60 3RD HARMONIC
-70
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
FFT PLOT (fIN = 7.5MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)
0
SNR = 57.7dB
-10 SINAD = 57.5dB
-20 THD = -71.8dBc
SFDR = 74.4dBc
-30
-40 2ND HARMONIC
-50
-60
3RD HARMONIC
-70
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
FFT PLOT (fIN = 19.99MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
0
SNR = 58.5dB
-10 SINAD = 58.4dB
-20 THD = -73.7dBc
SFDR = 75.9dBc
-30
-40 2ND HARMONIC
-50
3RD HARMONIC
-60
-70
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
FFT PLOT (fIN = 19.99MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)
0
SNR = 57.7dB
-10 SINAD = 57.2dB
-20 THD = -67dBc
SFDR = 67.7dBc
-30
-40 2ND HARMONIC
-50 3RD HARMONIC
-60
-70
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
UNDERSAMPLING FFT PLOT (fIN = 50.12MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
0
SNR = 57.9dB
-10 SINAD = 56.7dB
-20 THD = -71.3dBc
SFDR = 71.1dBc
-30
-40 2ND HARMONIC
-50
-60 3RD HARMONIC
-70
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
TWO-TONE INTERMODULATION
(8192-POINT IMD, DIFFERENTIAL INPUT)
0
-10
f1 = 38MHz AT -6.5dB FS
f2 = 42MHz AT -6.5dB FS
f2
-20 f1
-30
-40
-50 2ND ORDER IMD
-60
-70 3RD ORDER IMD
-80
-90
-100
0
10 20 30 40 50
ANALOG INPUT FREQUENCY (MHz)
60
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
80
DIFFERENTIAL
74
68
SINGLE-ENDED
62
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
60
58 DIFFERENTIAL
SINGLE-ENDED
56
54
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
-50
-56
-62 SINGLE-ENDED
-68
56 52 -74 DIFFERENTIAL
50
1
10
ANALOG INPUT FREQUENCY (MHz)
100
50
1
10
ANALOG INPUT FREQUENCY (MHz)
100
-80
1
10
ANALOG INPUT FREQUENCY (MHz)
100
_______________________________________________________________________________________ 5
5 Page 
10-Bit, 105Msps, Single +3.3V, Low-Power
ADC with Internal Reference
The MAX1449 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference out-
put REFOUT can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider, if an application
requires a reduced full-scale range. For stability pur-
poses it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is con-
nected to GND thereby deactivating the on-chip buffers
of REFP, COM, and REFN. With their buffers shut down,
these pins become high impedance and can be driven
by external reference sources.
Clock Input (CLK)
The MAX1449’s CLK input accepts CMOS-compatible
clock signals. Since the inter-stage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR per-
formance of the ADC as follows:
SNR = 20 × log (0.5 × π × fIN × tAJ)
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1449 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical
Characteristics. (See Figures 3 (3a, 3b) and 4 (4a, 4b)
for the relationship between spurious-free dynamic
range (SFDR), signal-to-noise ratio (SNR), total harmon-
ic distortion (THD), or signal-to-noise plus distortion
(SINAD) versus duty cycle.)
Output Enable (OE), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS logic-compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD high, the digital outputs
enter a high-impedance state. If OE is held low with PD
high, the outputs are latched at the last value prior to
the power down.
The capacitive load on the digital outputs D0 through D9
should be kept as low as possible (<15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1449, thereby degrading its
dynamic performance. The use of buffers on the digital
outputs of the ADC can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1449, small series
resistors (e.g., 100Ω) may be added to the digital output
paths, close to the ADC. Figure 5 displays the timing
relationship between output enable and data output valid
as well as power-down/wake-up and data output valid.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1449
samples at the falling edge of the input clock. Output
Table 1. MAX1449 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE*
VREF × 511/512
VREF × 510/512
VREF × 1/512
0
- VREF × 1/512
- VREF × 511/512
- VREF × 512/512
*VREF = VREFP = VREFN
DIFFERENTIAL INPUT
+Full Scale -1LSB
+Full Scale -2LSB
+1LSB
Bipolar Zero
-1LSB
Negative Full Scale + 1LSB
Negative Full Scale
STRAIGHT OFFSET BINARY
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1449.PDF ] | |
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