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PDF MAX1444 Data sheet ( Hoja de datos )
| Número de pieza | MAX1444 | |
| Descripción | 10-Bit / 40Msps / 3.0V / Low-Power ADC with Internal Reference | |
| Fabricantes | Maxim Integrated | |
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19-1745; Rev 1; 11/03
EVAALVUAAILTAIOBNLEKIT
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
General Description
The MAX1444 10-bit, 3V analog-to-digital converter
(ADC) features a pipelined 10-stage ADC architecture
with fully differential wideband track-and-hold (T/H)
input and digital error correction incorporating a fully
differential signal path. This ADC is optimized for low-
power, high dynamic performance applications in
imaging and digital communications. The MAX1444
operates from a single 2.7V to 3.6V supply, consuming
only 57mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differ-
ential input stage has a 400MHz -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1444 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible refer-
ence structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Higher speed, pin-compatible versions of the MAX1444
are also available. Please refer to the MAX1446 data
sheet (60Msps) and the MAX1448 data sheet
(80Msps).
The MAX1444 has parallel, offset binary, CMOS-com-
patible three-state outputs that can be operated from
1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5x5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
Features
o Single 3.0V Operation
o Excellent Dynamic Performance
59.5dB SNR at fIN = 20MHz
74dBc SFDR at fIN = 20MHz
o Low Power
19mA (Normal Operation)
5µA (Shutdown Mode)
o Fully Differential Analog Input
o Wide 2Vp-p Differential Input Voltage Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o CMOS-Compatible Three-State Outputs
o 32-Pin TQFP Package
o Evaluation Kit Available
PART
MAX1444EHJ
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Pin Configuration
TOP VIEW
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
REFN 1
COM 2
VDD 3
GND 4
GND 5
IN+ 6
IN- 7
GND 8
32 31 30 29 28 27 26 25
MAX1444
24 D4
23 OGND
22 T.P.
21 OVDD
20 D5
19 D6
18 D7
17 D8
9 10 11 12 13 14 15 16
Functional Diagram appears at end of data sheet.
TQFP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to
REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN
to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
cal values are at TA = +25°C.)
PARAMETER
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
SYMBOL
VHYST
IIH
IIL
CIN
CONDITIONS
VIH = VDD = OVDD
VIL = 0
VOL ISINK = 200µA
Output Voltage High
VOH ISOURCE = 200µA
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE Fall to Output Enable
OE Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-up Time
ILEAK
COUT
OE = OVDD
OE = OVDD
VDD
OVDD
IVDD
IOVDD
PSRR
Operating, fIN = 19.91MHz at -0.5dBFS
Shutdown, clock idle, PD = OE = OVDD
Operating, fIN = 19.91MHz at -0.5dBFS
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
tDO
tENABLE
tDISABLE
tCH
tCL
tWAKE
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 25ns
Figure 6, clock period 25ns
(Note 4)
MIN TYP
0.1
5
OVDD -
0.2
5
2.7 3.0
1.7 3.0
19
4
4.5
1
±0.1
±0.1
5
10
15
12.5 ±3.8
12.5 ±3.8
1.7
MAX
±5
±5
0.2
±10
3.6
3.6
27
15
20
8
UNITS
V
µA
pF
V
V
µA
pF
V
V
mA
µA
mA
µA
mV/V
%/V
ns
ns
ns
ns
ns
µs
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH / VIL.
Note 4: REFIN is driven externally. REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________ 5
5 Page 
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
Detailed Description
The MAX1444 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a
1-bit resolution.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b). Switches S2a and S2b set the common
mode for the amplifier input. The resulting differential
MDAC
VIN
T/H Σ
FLASH
ADC
DAC
1.5 BITS
x2 VOUT
VIN STAGE 1
STAGE 2
STAGE 10
DIGITAL ALIGNMENT LOGIC
10
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
voltage is held on C2a and C2b. Switches S4a, S4b,
S5a, S5b, S1, S2a, and S2b are then opened before
S3a, S3b, and S4c are closed, connecting capacitors
C1a and C1b to the amplifier output. This charges C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-chang-
ing input. The wide-input-bandwidth T/H amplifier
allows the MAX1444 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. The analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1444 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
INTERNAL
BIAS
S2a
COM
S5a
C1a S3a
S4a
IN+
C2a
S4c S1
OUT
IN-
S4b
C2b
OUT
C1b
S3b
S2b S5b
INTERNAL
BIAS
COM
CLK
TRACK
TRACK
HOLD
HOLD
INTERNAL
NON-OVERLAPPING
CLOCK SIGNALS
Figure 2. Internal T/H Circuit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1444.PDF ] | |
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