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PDF MAX1427 Data sheet ( Hoja de datos )
| Número de pieza | MAX1427 | |
| Descripción | 15-Bit / 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications | |
| Fabricantes | Maxim Integrated | |
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19-3022; Rev 0; 10/03
EVAALVUAAILTAIOBNLEKIT
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
General Description
The MAX1418 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1418 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.2dBFS, the MAX1418 allows for the
design of receivers with superior sensitivity.
The MAX1418 achieves two-tone, spurious-free dynamic
range (SFDR) of -85dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.6dB
and single-tone SFDR performance (SFDR1/SFDR2) of
88dBc/92dBc at fIN = 70MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1418 operates from an analog 5V and a digital
3V supply, features a 2.56VP-P full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1418 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1418 is manufactured in an 8mm x 8mm,
56-pin QFN package with exposed paddle (EP) for low
thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than fCLK/3. Unlike its baseband counter-
part MAX1419, the MAX1418 is optimized for input
frequencies greater than fCLK/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin Configuration appears at end of data sheet.
Features
o 65Msps Minimum Sampling Rate
o -78.2dBFS Noise Floor
o Excellent Dynamic Performance
73.6dB SNR at fIN = 70MHz and AIN = -2dBFS
88dBc/92dBc Single-Tone SFDR1/SFDR2 at
fIN = 70MHz and AIN = -2dBFS
-85dB Multitone SFDR at fIN1 = 69MHz
and fIN2 = 71MHz
o Less than 0.25ps Sampling Jitter
o Fully Differential Analog Input Voltage Range of
2.56VP-P
o CMOS-Compatible Two’s-Complement Data Output
o Separate Data Valid Clock and Overrange Outputs
o Flexible-Input Clock Buffer
o EV Kit Available for MAX1418
(Order MAX1427EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1418ETN
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
56 QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418 65 IF
MAX1419
65 Baseband
MAX1427
80 Baseband
MAX1428*
MAX1429*
80 IF
100 Baseband
MAX1430*
100
IF
*Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 65.0117MHz SFDR1 = 87.8dBc
-20
fIN = 15.0010MHz
AIN = -1.97dBFS
SFDR2 = 94.7dBc
HD2 = -96.9dBc
SNR = 75dB
HD3 = -87.8dBc
-40
-60
-80
-100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 65.0117MHz SFDR1 = 86.55dBc
-20
fIN = 34.9997MHz
AIN = -1.98dBFS
SFDR2 = 93.5dBc
HD2 = -92.6dBc
SNR = 74.8dB
HD3 = -86.4dBc
-40
-60
-80
-100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 65.0117MHz
-20
fIN = 70.0015MHz
AIN = -2.02dBFS
SNR = 73.7dB
-40 SFDR1 = 85.6dBc
SFDR2 = 91.2dBc
HD2 = -85.6dBc
-60 HD3 = -96.9dBc
-80
-100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0
fCLK = 65.0117MHz
-20
fIN = 169.9992MHz
AIN = -6.01dBFS
SNR = 68.5dBc
-40 SFDR1 = 67.5dBc
SFDR2 = 82.1dBc
HD2 = -67.5dBc
-60 HD3 = -73.6dBc
-80
-100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -2dBFS)
77
76
75
74
73
72
71
70
69
68
5
25 45 65 85 105 125 145 165 185
fIN (MHz)
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -2dBFS)
105
95 SFDR2
85
75
SFDR1
65
55
5
25 45 65 85 105 125 145 165 185
fIN (MHz)
_______________________________________________________________________________________ 5
5 Page 
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
Detailed Description
Figure 1 provides an overview of the MAX1418 archi-
tecture. The MAX1418 employs an input T/H amplifier,
which has been optimized for low thermal noise and
low distortion. The high-impedance differential inputs to
the T/H amplifier (INP and INN) are self-biased at
4.17V, and support a full-scale differential input voltage
of 2.56VP-P. The output of the T/H amplifier is fed to a
multistage pipelined ADC core, which has also been
optimized to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock wave-
form and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The dif-
ferential clock inputs (CLKP and CLKN) are high-
impedance inputs, are self-biased at 2.4V, and support
differential clock waveforms from 0.5VP-P to 3.0VP-P.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logic,
which in turn, deliver the 15-bit output code in two’s-
complement format to digital output drivers. The output
drivers provide CMOS-compatible outputs with levels
programmable over a 2.3V to 3.5V range.
Analog Inputs and
Common Mode (INP, INN, CM)
The signal inputs to the MAX1418 (INP and INN) are
balanced differential inputs. This differential configura-
tion provides immunity to common-mode noise cou-
pling and rejection of even-order harmonic terms. The
differential signal inputs to the MAX1418 should be AC-
coupled and carefully balanced to achieve the best
dynamic performance (see the Applications Information
section for more detail). AC-coupling of the input signal
is easily accomplished because the MAX1418 inputs
are self-biasing as illustrated in Figure 2. Although the
T/H inputs are high impedance, the actual differential
input impedance is nominally 1kΩ because of the two
500Ω bias resistors connected from each input to the
common-mode reference.
AVCC GND DVCC DRVCC
INP
MAX1418
INN
INTERNAL
CM REFERENCE
T/H
MULTISTAGE
PIPELINE ADC CORE
CLKP
CLKN
CLOCK
BUFFER
INTERNAL
TIMING
CORRECTION
LOGIC + OUTPUT
BUFFERS
15
DAV
DATA BITS D0 THROUGH D14
Figure 1. Simplified MAX1418 Diagram
INP
1kΩ
CM
INN
T/H AMPLIFIER
500Ω BUFFER
500Ω
T/H AMPLIFIER
TO 1. QUANTIZER STAGE
INTERNAL REFERENCE
AND BIASING CIRCUIT
TO 1. QUANTIZER STAGE
Figure 2. Simplified Analog and Common-Mode Input Architecture
The CM pin provides a monitor of the input common-
mode self-bias potential. In most applications, in which
the input signal is AC-coupled, this pin is not connect-
ed. If DC-coupling of the input signal is required, this
pin may be used to construct a DC servo loop to con-
trol the input common-mode potential. See the
Applications Information section for more details.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1427.PDF ] | |
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