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PDF MAX1421 Data sheet ( Hoja de datos )

Número de pieza MAX1421
Descripción 12-Bit / 40Msps / +3.3V / Low-Power ADC with Internal Reference
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX1421 Hoja de datos, Descripción, Manual

19-1900; Rev 0; 5/01
12-Bit, 40Msps, +3.3V, Low-Power ADC
with Internal Reference
General Description
The MAX1421 is a +3.3V, 12-bit analog-to-digital con-
verter (ADC), featuring a fully-differential input,
pipelined, 12-stage ADC architecture with wideband
track-and-hold (T/H) and digital error correction incor-
porating a fully-differential signal path. The MAX1421 is
optimized for low-power, high-dynamic performance
applications in imaging and digital communications.
The converter operates from a single +3.3V supply,
consuming only 188mW while delivering a typical sig-
nal-to-noise ratio (SNR) of 66dB at an input frequency
of 15MHz and a sampling frequency of 40Msps. The
fully-differential input stage has a small signal -3dB
bandwidth of 400MHz and may be operated with sin-
gle-ended inputs.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal or externally
applied buffered or unbuffered reference for applica-
tions requiring increased accuracy or a different input
voltage range.
In addition to low operating power, the MAX1421 fea-
tures two power-down modes, a reference power-down
and a shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, resulting in
a typical 2mA supply current reduction. For idle peri-
ods, a full shutdown mode is available to maximize
power savings.
The MAX1421 provides parallel, offset binary, CMOS-
compatible three-state outputs.
The MAX1421 is available in a 7mm x 7mm, 48-pin
TQFP package, and is specified over the commercial
(0°C to +70°C) and the extended industrial (-40°C to
+85°C) temperature ranges.
Pin-compatible higher- and lower-speed versions of the
MAX1421 are also available. Please refer to the
MAX1420 data sheet for a frequency of 60Msps and
the MAX1422 data sheet for a frequency of 20Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
Radar
IF and Baseband Digitization
Features
o Single +3.3V Power Supply
o 67dB SNR at fIN = 5MHz
o 66dB SNR at fIN = 15MHz
o Internal, +2.048V Precision Bandgap Reference
o Differential, Wideband Input T/H Amplifier
o Power-Down Modes
180mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
o Space-Saving 48-Pin TQFP Package
PART
MAX1421CCM
MAX1421ECM
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP
48 TQFP
Pin Configuration
AGND
AVDD
AVDD
AGND
AGND
INP
INN
AGND
AGND
AVDD
AVDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
MAX1421
36 D9
35 D8
34 D7
33 D6
32 DVDD
31 DVDD
30 DGND
29 DGND
28 D5
27 D4
26 D3
25 D2
Functional Diagram appears at end of data sheet.
48-TQFP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1421 pdf
12-Bit, 40Msps, +3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Pipeline Delay (Latency)
Aperture Delay
Aperture Jitter
Data Output Delay
Bus Enable Time
Bus Disable Time
Figure 5
tAD Figure 9
tAJ Figure 9
tOD Figure 5
tBE Figure 4
tBD Figure 4
7 fCLK
cycles
2 ns
2 ps
5 10 14 ns
5 ns
5 ns
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External +2.048V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1421.
Note 6: VDIFF = VREFP - VREFN
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: VREFIN is internally biased to +2.048V through a 10kresistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ± 5% change in VAVDD using the internal reference.
Typical Operating Characteristics
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output
load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
0
fIN = 7.5439934MHz
AIN = -0.45dB FS
-20
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
0
fIN = 19.9047628MHz
AIN = -0.50dB FS
-20
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
0
fIN = 38.5440183MHz
AIN = -0.49dB FS
-20
-40 -40 -40
HD2
HD2 HD3
-60
HD2 HD3
-60
-60
HD3
-80 -80 -80
-100 -100 -100
-120
0
5 10 15
ANALOG INPUT FREQUENCY (MHz)
20
-120
0
5 10 15
ANALOG INPUT FREQUENCY (MHz)
20
-120
0
5 10 15
ANALOG INPUT FREQUENCY (MHz)
20
_______________________________________________________________________________________ 5

5 Page





MAX1421 arduino
12-Bit, 40Msps, +3.3V, Low-Power ADC
with Internal Reference
AVDD
R
R
AVDD
2
R
AVDD
4
R
50
0.22µF
MAX4284
AVDD
2
50
R 0.22µF
MAX4284
AVDD
4
R
50
0.22µF
R
R AGND
+1V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
( )CML
AVDD
2
1nF
( )REFP
AVDD + 1V
2
1nF
MAX1421
( )REFN AVDD + 1V
2
1nF
REFIN
The MAX1421 provides three modes of reference oper-
ation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22µF, in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1421s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
SNRdB
=
20
×
log10
 2π
×
1
ƒIN
×
tAJ 
where fIN represents the analog input frequency and
tAJ is the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AVDD / 2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
______________________________________________________________________________________ 11

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