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PDF MAX1420ECM Data sheet ( Hoja de datos )

Número de pieza MAX1420ECM
Descripción 12-Bit / 60Msps / +3.3V / Low-Power ADC with Internal Reference
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX1420ECM Hoja de datos, Descripción, Manual

19-1981; Rev 0; 5/01
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
General Description
The MAX1420, +3.3V, 12-bit analog-to-digital converter
(ADC) features a fully-differential input, pipelined, 12-
stage ADC architecture with wideband track-and-hold
(T/H) and digital error correction, incorporating a fully-
differential signal path. The MAX1420 is optimized for
low-power, high dynamic performance applications in
imaging and digital communications. The converter
operates from a single +3.3V supply, and consumes
only 221mW. The fully-differential input stage has a
small signal -3dB bandwidth of 400MHz and may be
operated with single-ended inputs.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal reference, or
externally applied buffered or unbuffered reference for
applications that require increased accuracy and a dif-
ferent input voltage range.
In addition to low operating power, the MAX1420 fea-
tures two power-down modes: reference power-down
and shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, which
results in a typical 2mA supply current reduction. A full
shutdown mode is available to maximize power savings
during idle periods.
The MAX1420 provides parallel, offset binary, CMOS-
compatible three-state outputs.
The MAX1420 is available in a 7mm 7mm, 48-pin
TQFP package, and is specified over the commercial
(0°C to +70°C) and the extended industrial (-40°C to
+85°C) temperature range.
Pin-compatible lower speed versions of the MAX1420
are also available. Please refer to the MAX1421 data
sheet for 40Msps and the MAX1422 data sheet for
20Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
IR Focal Plane Arrays
Radar
IF & Baseband Digitization
Features
o +3.3V Single Power Supply
o 67dB SNR at fIN = 5MHz
o 66dB SNR at fIN = 15MHz
o Internal +2.048V Precision Bandgap Reference
o Differential, Wideband Input T/H Amplifier
o Power-Down Modes:
218mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
o Space-Saving 48-Pin TQFP Package
PART
MAX1420CCM
MAX1420ECM
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP
48 TQFP
AGND
AVDD
AVDD
AGND
AGND
INP
INN
AGND
AGND
AVDD
AVDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
Pin Configuration
MAX1420
36 D9
35 D8
34 D7
33 D6
32 DVDD
31 DVDD
30 DGND
29 DGND
28 D5
27 D4
26 D3
25 D2
Functional diagram appears at end of data sheet.
48-TQFP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1420ECM pdf
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK =
62.5MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Power Dissipation In Shutdown
Power-Supply Rejection Ratio
PDISS
PSRR
PD = VDVDD
(Note 9)
10 µW
±1 mV/V
TIMING CHARACTERISTICS
Maximum Clock Frequency
Clock High
Clock Low
fCLK
tCH
tCL
Figure 6, clock period 16.667ns
Figure 6, clock period 16.667ns
60
8.33
8.33
MHz
ns
ns
Pipeline Delay (Latency)
Figure 6
7
fCLK
cycles
Aperture Delay
Aperture Jitter
Data Output Delay
Bus Enable Time
Bus Disable Time
tAD Figure 10
tAJ Figure 10
tOD Figure 6
tBE Figure 5
tBD Figure 5
2 ns
2 ps
5 10 14 ns
5 ns
5 ns
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External +2.048V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1420.
Note 6: VDIFF = VREFP - VREFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: VREFIN is internally biased to +2.048V through a 10kresistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in VAVDD, using the internal reference.
Typical Operating Characteristics
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty
cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
0
fIN = 5.5449583MHz
-20
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
0
fIN = 13.4119138MHz
-20
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
0
fIN = 37.701219MHz
-20
-40
-60 HD2 HD3
-80
-40
-60
-80
HD2
HD3
-40
HD3
-60
-80
HD2
-100 -100 -100
-120
0
5 10 15 20 25
ANALOG INPUT FREQUENCY (MHz)
30
-120
0
5 10 15 20 25
ANALOG INPUT FREQUENCY (MHz)
30
-120
0
5 10 15 20 25
ANALOG INPUT FREQUENCY (MHz)
30
_______________________________________________________________________________________ 5

5 Page





MAX1420ECM arduino
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
AVDD
R
R
50
( )CML
AVDD
2
0.22µF
1nF
AVDD
2
MAX4284
50
( )REFP
AVDD
2
0.5V
R
0.22µF
R
1nF
AVDD
2
MAX1420
AVDD
4
R
50
R MAX4284
( )REFN AVDD- 0.5V
2
0.22µF
1nF
AVDD
4
R
REFIN
R AGND
0.5V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
cations that require increased accuracy and a different
input voltage range.
The MAX1420 provides three modes of reference oper-
ation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN and CML with a capacitor
network of 0.22µF in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, thereby deactivating the on-chip
buffers of REFP, CML, and REFN. With their buffers
shut down, these nodes become high impedance and
can be driven by external reference sources, as shown
in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1420s CLK and CLK inputs accept both dif-
ferential and single-ended input operation and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). Sampling
occurs on the rising edge of the clock signal, requiring
this edge to have the lowest possible jitter. Any signifi-
cant aperture jitter would limit the SNR performance of
the ADC according to the following relationship:
SNRdB
=
20 × log10
2π
1
× fIN
×
tAJ
where fIN represents the analog input frequency and
tAJ is the aperture jitter. Clock jitter is especially critical
for high input frequency applications. The clock input
should always be considered as an analog signal and
routed away from any analog or digital signal lines.
The MAX1420 clock input operates with a voltage
threshold set to AVDD/2. Clock inputs must meet the
specifications for high and low periods as stated in the
Electrical Characteristics.
______________________________________________________________________________________ 11

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