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PDF MAX1419 Data sheet ( Hoja de datos )
| Número de pieza | MAX1419 | |
| Descripción | 15-Bit / 65Msps ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-3011; Rev 1; 2/04
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
General Description
The MAX1419 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1419 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -79.3dBFS, the MAX1427 allows for the
design of receivers with superior sensitivity.
The MAX1419 achieves two-tone, spurious-free dynamic
range (SFDR) of -91dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 76.2dB
and single-tone SFDR performance (SFDR1/SFDR2) of
93.1dBc/95.5dBc at fIN = 15MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1419 operates from an analog 5V and a digital
3V supply, features a 2.56VP-P full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
200MHz.
The MAX1419 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1419 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see the Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than fCLK/3. The MAX1419 is optimized for
input frequencies of less than fCLK/3.
Features
♦ 65Msps Minimum Sampling Rate
♦ -79.3dBFS Noise Floor
♦ Excellent Dynamic Performance
76.2dB SNR at fIN=15MHz and AIN = -1dBFS
93.1dBc/95.5dBc Single-Tone SFDR1/SFDR2 at
fIN = 15MHz and AIN = -1dBFS
-91dBc Multitone SFDR at fIN1 = 10MHz
and fIN2 = 15MHz
♦ Less than 0.25ps Sampling Jitter
♦ Fully Differential Analog Input Voltage Range of
2.56VP-P
♦ CMOS-Compatible Two’s-Complement Data Output
♦ Separate Data Valid Clock and Overrange Outputs
♦ Flexible-Input Clock Buffer
♦ EV Kit Available for the MAX1419
(Order MAX1427EVKIT)
Ordering Information
PART
MAX1419ETN
TEMP RANGE
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
56 Thin QFN-EP*
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin Configuration appears at end of data sheet.
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418
MAX1419
MAX1427
MAX1428*
MAX1429*
MAX1430*
65 IF
65 Baseband
80 Baseband
80 IF
100 Baseband
100 IF
*Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
0 00
fCLK = 65.0117MHz
fCLK = 65.0117MHz
fCLK = 65.0117MHz
-20
fIN = 10.0013MHz
AIN = -1.02dBFS
-20
fIN = 15.0010MHz
AIN = -0.98dBFS
-20
fIN = 25.0004MHz
AIN = -06dBFS
SNR = 76.8dB
SNR = 76.5dB
SNR = 76.3dB
-40
SFDR1 = 87.7dBc
SFDR2 = 98.3dBc
-40
SFDR1 = 89.1dBc
SFDR2 = 98.1dBc
-40 SFDR1 = 77.9dBc
SFDR2 = 92.3dBc
HD2 = 87.7dBc
HD2 = 94.8dBc
HD2 = 85.6dBc
-60
HD3 = 91.5dBc
-60
HD3 = 89dBc
-60 HD3 = 77.9dBc
-80 -80 -80
-100 -100 -100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
78
77
76
75
74
73
72
71
70
5
15 25 35 45 55 65
fIN (MHz)
FULL-SCALE-TO-NOISE RATIO vs.
ANALOG INPUT AMPLITUDE
(fCLK = 65.011712MHz, fIN = 15.0010MHz)
80
79
78
77
76
75
74
73
72
71
70
-70
-60 -50 -40 -30 -20 -10
ANALOG INPUT AMPLITUDE (dBFS)
0
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
100
-120
0
5 10 15 20 25 30
ANALOG INPUT FREQUENCY (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
-70
95
SFDR2
90
-75
-80
HD3
85
SFDR1
80
-85
HD2
-90
75 -95
70
5
15 25 35 45 55 65
fIN (MHz)
-100
5
15 25 35 45 55 65
fIN (MHz)
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE
(fCLK = 65.0117MHz, fIN = 15.0010MHz)
130
120 SFDR1 SFDR2
110
100
90
80
70
-70
-60 -50 -40 -30 -20 -10
ANALOG INPUT AMPLITUDE (dBFS)
0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fCLK = 65.0117MHz, fIN = 15.0010MHz)
-70
-80
-90 HD3
-100
-110
-120
-130 HD2
-140
-150
-70
-60 -50 -40 -30 -20 -10
ANALOG INPUT AMPLITUDE (dBFS)
0
_______________________________________________________________________________________ 5
5 Page 
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
• tDGV: Time from the rising edge of the clock until data
is guaranteed to be valid
• tSETUP: Time from data guaranteed valid until the ris-
ing edge of DAV
• tHOLD: Time from the rising edge of DAV until data is
no longer valid
• tCLKP: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
• tCLKN: Time from 50% point of the falling edge to the
50% point of the rising edge of the clock signal
The MAX1419 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
Digital Outputs (D0–D14, DAV, DOR)
The logic “high” level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) may be set in the
range of 2.3V to 3.5V. This is accomplished by setting
the voltage at the DVCC and DRVCC pins to the desired
logic-high level. Note that the DVCC and DRVCC volt-
ages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1419 should be kept as low as possible
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220Ω or less) between
the MAX1419 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in con-
trolling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illus-
trated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV may be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condi-
tion. If the input signal exceeds the positive or negative
full-scale range for the MAX1419, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an over-
range indication on a sample-by-sample basis.
Table 1. MAX1419 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
VREF + 0.64V
VREF - 0.64V
VREF
VREF
VREF - 0.64V
VREF + 0.64V
D14–D0
TWO’S COMPLEMENT CODE
011111111111111
(positive full scale)
000000000000000
(midscale + δ)
111111111111111
(midscale - δ)
100000000000000
(negative full scale)
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1419.PDF ] | |
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