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PDF MAX1402EAI Data sheet ( Hoja de datos )
| Número de pieza | MAX1402EAI | |
| Descripción | +5V / 18-Bit / Low-Power / Multichannel / Oversampling Sigma-Delta ADC | |
| Fabricantes | Maxim Integrated | |
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19-1423; Rev 0; 3/99
EVAALVUAAILTAIOBNLEKIT +5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
General Description
The MAX1402 low-power, multichannel, serial-output
analog-to-digital converter (ADC) features matched
200µA current sources for sensor excitation. This ADC
uses a sigma-delta modulator with a digital decimation
filter to achieve 16-bit accuracy. The digital filter’s user-
selectable decimation factor allows the conversion res-
olution to be reduced in exchange for a higher output
data rate. True 16-bit performance is achieved at an
output data rate of up to 480sps. In addition, the modu-
lator sampling frequency may be optimized for either
lowest power dissipation or highest throughput rate.
The MAX1402 operates from a +5V supply.
This device offers three fully differential input channels
that may be independently programmed with a gain
between +1V/V and +128V/V. Furthermore, it can com-
pensate an input-referred DC offset up to 117% of the
selected full-scale range. These three differential chan-
nels may also be configured to operate as five pseudo-
differential input channels. Two additional, fully
differential system-calibration channels are provided for
gain and offset error correction.
The MAX1402 may be configured to sequentially scan all
signal inputs and provide the results via the serial inter-
face with minimum communications overhead. When
used with a 2.4576MHz or 1.024MHz master clock, the
digital decimation filter can be programmed to produce
zeros in its frequency response at the line frequency and
associated harmonics, ensuring excellent line rejection
without the need for further post-filtering.
The MAX1402 is available in a 28-pin SSOP package.
Applications
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
PART
MAX1402CAI
MAX1402EAI
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
28 SSOP
SPI and QSPI are trademarks of Motorola, Inc.
Features
o 18-Bit Resolution, Sigma-Delta ADC
o 16-Bit Accuracy with No Missing Codes to 480sps
o Low Quiescent Current
250µA (operating mode)
2µA (power-down mode)
o Matched On-Board Current Sources (200µA) for
Sensor Excitation
o 3 Fully Differential or 5 Pseudo-Differential Signal
Input Channels
o 2 Additional, Fully Differential Calibration
Channels/Auxiliary Input Channels
o Programmable Gain and Offset
o Fully Differential Reference Inputs
o Converts Continuously or On Command
o Automatic Channel Scanning and Continuous
Data Output Mode
o Operates with +5V Analog Supply and +3V or +5V
Digital Supply
o 3-Wire Serial Interface—SPI™/QSPI™ Compatible
o 28-Pin SSOP Package
Pin Configuration
TOP VIEW
CLKIN 1
CLKOUT 2
CS 3
RESET 4
DS1 5
DS0 6
OUT2 7
OUT1 8
AGND 9
V+ 10
AIN1 11
AIN2 12
AIN3 13
AIN4 14
MAX1402
SSOP
28 SCLK
27 DIN
26 DOUT
25 INT
24 VDD
23 DGND
22 CALOFF+
21 CALOFF-
20 REFIN+
19 REFIN-
18 CALGAIN+
17 CALGAIN-
16 AIN6
15 AIN5
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C.)
PARAMETER
POWER REQUIREMENTS
V+ Voltage
VDD Voltage
Power-Supply Rejection V+
(Note 16)
SYMBOL
CONDITIONS
V+ For specified performance
VDD
PSR
MIN TYP MAX UNITS
4.75 5.25
2.7 5.25
(Note 17)
V
V
dB
ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxil-
iary currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
V+ Standby Current (Note 18)
PD bit = 1, external clock stopped
1 10 µA
Normal mode,
MF1 = 0,
MF0 = 0
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
175 210
370 420
250 300
µA
610 700
V+ Current
2X mode,
MF1 = 0,
MF0 = 1
IV+
4X mode,
MF1 = 1,
MF0 = 0
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
245
610
0.42 0.55
1.2 1.5
0.42
1.2
1.8 2.2
mA
4.8 6
8X mode,
MF1 = 1,
MF0 = 1
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
1.8
4.8
1.8 2.2
4.8 6
DIGITAL POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxiliary
currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
VDD Standby Current (Note 18)
3.3V Digital Supply Current
5V Digital Supply Current
PD bit = 1, external clock stopped
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
2.4576MHz
2X mode,
MF1 = 0, MF0 = 1
IDD
4X mode,
MF1 = 1, MF0 = 0
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
8X mode,
MF1 = 1, MF0 = 1
1.024MHz
2.4576MHz
Normal mode,
MF1 = 0, MF0 = 0
IDD
2X mode,
MF1 = 0, MF0 = 1
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
1 10 µA
70 200
µA
150 300
0.08
0.17 0.35
0.11
mA
0.22 0.40
0.15
0.32 0.45
115 300
µA
235 450
0.13
mA
0.28 0.5
_______________________________________________________________________________________ 5
5 Page 
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Pin Description
PIN NAME
FUNCTION
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
1
CLKIN
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT uncon-
nected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
2 CLKOUT CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
Chip-Select Input. Active-low logic input used to enable the digital interface. With CS hard-wired low, the
3
CS
MAX1402 operates in its 3-wire interface mode with SCLK, DIN and DOUT used to interface to the device.
CS is used either to select the device in systems with more than one device on the serial bus, or as a
frame-synchronization signal for the MAX1402 when a continuous SCLK is used.
4
RESET
Active-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter and analog modu-
lator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
5
DS1
Digital Input for Auxiliary Data Input Bit 1. The status of this bit is reflected in the output data by bit D4.
Used to communicate the status of DS1 via the serial interface.
6
DS0
Digital Input for Auxiliary Data Input Bit 0. The status of this bit is reflected in the output data by bit D3.
Used to communicate the status of DS0 via the serial interface.
7
OUT2
Transducer Excitation Current Source 2
8
OUT1
Transducer Excitation Current Source 1
9
AGND
Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
10 V+ Analog Positive Supply Voltage (+4.75V to +5.25V).
11
AIN1
Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN1/AIN2 differential analog input pair (see Communications Register section).
12
AIN2
Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN1/AIN2 differential analog input pair (see Communications Register section).
13
AIN3
Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN3/AIN4 differential analog input pair (see Communications Register section).
14
AIN4
Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN3/AIN4 differential analog input pair (see Communications Register section).
15
AIN5
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6
(see Communications Register section).
16
AIN6
Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see Communications Register section).
______________________________________________________________________________________ 11
11 Page | ||
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