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PDF MAX1400CAI Data sheet ( Hoja de datos )

Número de pieza MAX1400CAI
Descripción Oversampling (Sigma-Delta) ADC
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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19-1430; Rev 1; 7/02
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
General Description
The MAX1400 18-bit, low-power, multichannel, serial-
output ADC uses a sigma-delta modulator with a digital
decimation filter to achieve true 16-bit accuracy. The
user-selectable decimation factor of the digital filter
allows the conversion resolution to be reduced in
exchange for a higher output data rate. The device
achieves true 16-bit performance at an output data rate of
up to 480sps. In addition, the modulator sampling
frequency may be optimized for either lowest power
dissipation or highest throughput rate. The MAX1400
operates from +5V.
This device offers three fully differential input channels
that can be independently programmed with a gain
between +1V/V and +128V/V. Furthermore, it can com-
pensate an input-referred DC offset (such as system off-
set) up to 117% of the selected full-scale range. These
three differential channels may also be configured to
operate as five pseudo-differential input channels. Two
additional, fully differential system-calibration channels
are provided for gain and offset error correction. External
access is provided to the multiplexer (mux) output to
facilitate additional signal processing.
The MAX1400 can be configured to scan all signal inputs
sequentially and provide the results through the serial
interface with minimum communications overhead. When
used with a 2.4576MHz or 1.024MHz master clock, the
digital decimation filter can be programmed to produce
zeros in its frequency response at the line fre-
quency and associated harmonics, ensuring excellent
line rejection without the need for further post-filtering.
The MAX1400 comes in a 28-pin SSOP package.
Applications
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
PART
MAX1400CAI
MAX1400EAI
Ordering Information
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
28 SSOP
SPI and QSPI are trademarks of Motorola, Inc.
Features
o 18-Bit Resolution, Sigma-Delta ADC
o 16-Bit Performance with No Missing Codes
to 480sps
o Low Quiescent Current
250µA (operating mode)
2µA (power-down mode)
o 3 Fully Differential or 5 Pseudo-Differential Signal
Input Channels
o 2 Additional Fully Differential Calibration
Channels/Auxiliary Input Channels
o Access to the Mux Output/ADC Input
o Programmable Gain and Offset
o Fully Differential Reference Inputs
o Converts Continuously or On Command
o Automatic Channel Scanning and Continuous
Data Output Mode
o Operates with +5V Analog Supply and
+3V or +5V Digital Supply
o SPI™/QSPI™-Compatible 3-Wire Serial Interface
o 28-Pin SSOP Package
Pin Configuration
TOP VIEW
CLKIN 1
CLKOUT 2
CS 3
RESET 4
MUXOUT+ 5
MUXOUT- 6
ADCIN+ 7
ADCIN- 8
AGND 9
V+ 10
AIN1 11
AIN2 12
AIN3 13
AIN4 14
MAX1400
SSOP
28 SCLK
27 DIN
26 DOUT
25 INT
24 VDD
23 DGND
22 CALOFF+
21 CALOFF-
20 REFIN+
19 REFIN-
18 CALGAIN+
17 CALGAIN-
16 AIN6
15 AIN5
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1400CAI pdf
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out currents
disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
V+ Standby Current
V+ Current
PD bit = 1, external clock stopped (Note 18)
Normal mode,
MF1 = 0,
MF0 = 0
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
2X mode,
MF1 = 0,
MF0 = 1
IV+
4X mode,
MF1 = 1,
MF0 = 0
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
8X mode,
MF1 = 1,
MF0 = 1
Buffers off
1.024MHz
Buffers on
Buffers off
2.4576MHz
Buffers on
1 10 µA
175 210
370 420
250 300
µA
610 700
245
610
0.42 0.55
1.2 1.5
0.42
1.2
1.8 2.2
mA
4.8 6
1.8
4.8
1.8 2.2
4.8 6
DIGITAL POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external MCLKIN, burn-out currents
disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
VDD Standby Current
3.3V Digital Supply Current
PD bit = 1, external clock stopped (Note 18)
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
2.4576MHz
2X mode,
MF1 = 0, MF0 = 1
IDD
4X mode,
MF1 = 1, MF0 = 0
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
8X mode,
MF1 = 1, MF0 = 1
1.024MHz
2.4576MHz
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
2.4576MHz
1 10 µA
70 200
µA
150 300
0.08
0.17 0.35
0.11
mA
0.22 0.40
0.15
0.32 0.45
150 300
µA
235 450
5V Digital Supply Current
2X mode,
MF1 = 0, MF0 = 1
IDD
4X mode,
MF1 = 1, MF0 = 0
8X mode,
MF1 = 1, MF0 = 1
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
0.13
0.28 0.50
0.17
mA
0.36 0.60
0.24
0.53 0.80
_______________________________________________________________________________________ 5

5 Page





MAX1400CAI arduino
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________Detailed Description
Circuit Description
The MAX1400 is a low-power, multichannel, serial-
output, sigma-delta ADC designed for applications with
a wide dynamic range, such as weigh scales and pres-
sure transducers. The functional block diagram in
Figure 2 contains a switching network, a modulator, a
PGA, two buffers, an oscillator, an on-chip digital filter,
and a bidirectional serial communications port.
Three fully-differential input channels feed into the
switching network. Each channel may be independent-
ly programmed with a gain between +1V/V and
+128V/V. These three differential channels may also be
configured to operate as five pseudo-differential input
channels. Two additional, fully differential system-cali-
bration channels allow system gain and offset error to
be measured. These system-calibration channels can
be used as additional differential signal channels when
dedicated gain and offset error correction channels are
not required.
Two chopper-stabilized buffers are available to isolate
the selected inputs from the capacitive loading of the
PGA and modulator. Three independent DACs provide
compensation for the DC component of the input signal
on each of the differential input channels.
The sigma-delta modulator converts the input signal into
a digital pulse train whose average duty cycle represents
the digitized signal information. The pulse train is then
processed by a digital decimation filter, resulting in a
conversion accuracy exceeding 16 bits. The digital filter’s
decimation factor is user-selectable, which allows the
conversion result’s resolution to be reduced to achieve a
higher output data rate. When used with 2.4576MHz or
1.024MHz master clocks, the decimation filter can be
programmed to produce zeros in its frequency response
at the line frequency and associated harmonics. This
ensures excellent line rejection without the need for fur-
ther post-filtering. In addition, the modulator sampling
frequency can be optimized for either lowest power dis-
sipation or highest output data rate.
The MAX1400 can be configured to sequentially scan
all signal inputs and to transmit the results through the
serial interface with minimum communications over-
head. The output word contains a result identification
tag to indicate the source of each conversion result.
ADCIN+
MUXOUT+
CALOFF+
CALGAIN+
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
CALOFF-
CALGAIN-
MUXOUT-
ADCIN-
REFIN+
REFIN-
SWITCHING
NETWORK
V+
AGND
BUFFER
MAX1400
DIVIDER
CLOCK
GEN
BUFFER
PGA
MODULATOR
DIGITAL
FILTER
DAC
INTERFACE
AND CONTROL
CLKIN
CLKOUT
VDD
DGND
V+
AGND
SCLK
DIN
DOUT
INT
CS
RESET
Figure 2. Functional Diagram
______________________________________________________________________________________ 11

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