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PDF MAX1280 Data sheet ( Hoja de datos )
| Número de pieza | MAX1280 | |
| Descripción | Serial 12-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
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19-1684; Rev 2; 10/10
EVAALVUAAILTAIOBNLEKIT
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1280/MAX1281 12-bit ADCs combine an 8-chan-
nel analog-input multiplexer, high-bandwidth track/hold,
and serial interface with high conversion speed and low
power consumption. The MAX1280 operates from a single
+4.5V to +5.5V supply; the MAX1281 operates from a sin-
gle +2.7V to +3.6V supply. Both devices’ analog inputs
are software configurable for unipolar/bipolar and single-
ended/pseudo-differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1280/
MAX1281 use an external serial-interface clock to per-
form successive-approximation analog-to-digital con-
versions. Both parts feature an internal +2.5V reference
and a reference-buffer amplifier with a ±1.5% voltage-
adjustment range. An external reference with a 1V to
VDD1 range may also be used.
The MAX1280/MAX1281 provide a hard-wired SHDN
pin and four software-selectable power modes (normal
operation, reduced power, fast power-down, and full
power-down). These devices can be programmed to
automatically shut down at the end of a conversion or to
operate with reduced power. When using the power-
down modes, accessing the serial interface automatical-
ly powers up the devices, and the quick turn-on time
allows them to be powered down between all conver-
sions. This technique can cut supply current to under
100µA at reduced sampling rates.
The MAX1280/MAX1281 are available in 20-pin TSSOP
packages. These devices are higher-speed versions of
the MAX146/MAX147 (for more information, see the
respective data sheet).
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
♦ 8-Channel Single-Ended or 4-Channel
Pseudo-Differential Inputs
♦ Internal Multiplexer and Track/Hold
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1280)
+2.7V to +3.6V (MAX1281)
♦ Internal +2.5V Reference
♦ 400ksps Sampling Rate (MAX1280)
♦ Low Power 2.5mA (400ksps)
1.3mA (Reduced-Power Mode)
0.9mA (Fast Power-Down Mode)
2µA (Full Power-Down)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin TSSOP Package
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
MAX1280BCUP+ 0°C to +70°C 20 TSSOP
MAX1280BEUP+ -40°C to +85°C 20 TSSOP
MAX1281BCUP+ 0°C to +70°C 20 TSSOP
MAX1281BEUP+ -40°C to +85°C 20 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
INL
(LSB)
±1
±1
±1
±1
Pin Configuration
TOP VIEW
+
CH0 1
CH1 2
CH2 3
CH3 4
CH4 5
MAX1280
MAX1281
CH5 6
CH6 7
CH7 8
COM 9
SHDN 10
20 VDD1
19 VDD2
18 SCLK
17 CS
16 DIN
15 SSTRB
14 DOUT
13 GND
12 REFADJ
11 REF
TSSOP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1281 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CONVERSION RATE
Conversion Time (Note 5)
tCONV Normal operating mode
3.3 µs
Track/Hold Acquisition Time
tACQ Normal operating mode
625 ns
Aperture Delay
10 ns
Aperture Jitter
< 50
ps
Serial Clock Frequency
fSCLK
Duty Cycle
ANALOG INPUTS (CH7–CH0, COM)
Input Voltage Range, Single-
Ended and Differential (Note 6)
VCH_
Normal operating mode
Unipolar, VCOM = 0
Bipolar, VCOM or VCH_ = VREF/2,
referenced to COM or CH_
0.5 4.8 MHz
40 60 %
VREF
±VREF/2
V
Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
On/off leakage current, VCH_ = 0 or VDD1
±0.001 ±1
18
µA
pF
REF Output Voltage
REF Short-Circuit Current
VREF TA = +25°C
2.480 2.500 2.520
15
V
mA
REF Output Temperature
Coefficient
TC VREF
±15 ppm/°C
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
0 to 0.75mA output load
0.1 2.0
mV/mA
4.7 10 µF
0.01 10 µF
REFADJ Output Voltage
REFADJ Input Range
For small adjustments, from 1.22V
1.22 V
±50 mV
REFADJ Buffer Disable
Threshold
To power down the internal reference
1.33
VDD1 - 1
V
Buffer Voltage Gain
EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF)
2.05 V/V
REF Input Voltage Range
(Note 8)
1.0
VDD1 +
50mV
V
REF Input Current
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
VHYST
Input Leakage
IIN
Input Capacitance
CIN
VREF = 2.500V, fSCLK = 4.8MHz
VREF = 2.500V, fSCLK = 0
In power-down, fSCLK = 0
VIN = 0 or VDD2
200 350
320
5
2.0
0.8
0.2
±1
15
µA
V
V
V
µA
pF
_______________________________________________________________________________________ 5
5 Page 
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Detailed Description
The MAX1280/MAX1281 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to microprocessors
(µPs). Figure 3 shows a functional diagram of the
MAX1280/MAX1281.
Pseudo-Differential Input
The equivalent input circuit of Figure 4 shows the
MAX1280/MAX1281’s input architecture, which is com-
posed of a T/H, input multiplexer, input comparator,
switched-capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 2 and 3.
The MAX1280/MAX1281 input configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) is connected to the sampling capacitor
while converting and must remain stable within ±0.5LSB
(±0.1LSB for best results) with respect to GND during a
conversion.
If a varying signal is applied to the selected IN-, its ampli-
tude and frequency must be limited to maintain accuracy.
The following equations determine the relationship
between the maximum signal amplitude and its frequency
in order to maintain ±0.5LSB accuracy. Assuming a sinu-
soidal signal at IN-, the input voltage is determined by:
( )νIN- = VIN- sin(2πft)
The maximum voltage variation is determined by:
( )max dνIN-
dt
=
VIN-
2πf ≤
1LSB
tCONV
=
VREF
212 tCONV
A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB
of error when using a +2.5V reference voltage and a
2.5µs conversion time (15/fSCLK). When a DC reference
voltage is used at IN-, connect a 0.1µF capacitor to
GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 12-bit
resolution. This action is equivalent to transferring a
12pF x (VIN+ - VIN-) charge from CHOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
CS 17
SCLK 18
DIN
SHDN
16
10
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
CH0 1
CH1 2
CH2 3
CH3 4
CH4 5
CH5 6
CH6 7
CH7 8
COM 9
REFADJ 12
REF 11
OUTPUT 14 DOUT
SHIFT
REGISTER
15
SSTRB
ANALOG
INPUT
MUX
T/H
CLOCK
IN 12-BIT
SAR
ADC OUT
REF
20 VDD1
A ≈ 2.05*
+1.22V 17kΩ
REFERENCE
19 VDD2
13 GND
+2.500V
MAX1280
MAX1281
Figure 3. Functional Diagram
GND
CAPACITATIVE
REF DAC
INPUT
CH0 MUX
CH1
CHOLD
12pF
ZERO
COMPARATOR
CH2
CH3 CSWITCH*
CH4 6pF
CH5
HOLD
RIN
800Ω
CH6
CH7
TRACK AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
VDD1/2
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
*INCLUDES ALL INPUT PARASITICS
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MAX1280.PDF ] | |
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