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PDF MAX127 Data sheet ( Hoja de datos )
| Número de pieza | MAX127 | |
| Descripción | Multirange / +5V / 12-Bit DAS with 2-Wire Serial Interface | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX127 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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MAX127/MAX128
EVALUATION KIT AVAILABLE
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
General Description
The MAX127/MAX128 are multirange, 12-bit data acquisi-
tion systems (DAS) that require only a single +5V supply
for operation, yet accept signals at their analog inputs
that may span above the power-supply rail and below
ground. These systems provide eight analog input chan-
nels that are independently software programmable for
a variety of ranges: ±10V, ±5V, 0 to +10V, 0 to +5V for
the MAX127; and ±VREF, ±VREF/2, 0 to +VREF, 0 to
+VREF/2 for the MAX128. This range switching increases
the effective dynamic range to 14 bits and provides the
flexibility to interface 4–20mA, ±12V, and ±15V-powered
sensors directly to a single +5V system. In addition, these
converters are fault protected to ±16.5V; a fault condition
on any channel will not affect the conversion result of the
selected channel. Other features include a 5MHz band-
width track/hold, an 8ksps throughput rate, and the option
of an internal 4.096V or external reference.
The MAX127/MAX128 feature a 2-wire, I2C-compatible
serial interface that allows communication among multiple
devices using SDA and SCL lines.
A hardware shutdown input (SHDN) and two softwarepro-
grammable power-down modes (standby and full power-
down) are provided for low-current shutdown between
conversions. In standby mode, the reference buffer
remains active, eliminating startup delays.
The MAX127/MAX128 are available in 24-pin narrow
PDIP or space-saving 28-pin SSOP packages.
Applications
●● Industrial Control Systems
●● Data-Acquisition Systems
●● Robotics
●● Automatic Testing
●● Battery-Powered Instruments
●● Medical Instruments
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX127ACNG+ 0°C to +70°C 24 Narrow PDIP
MAX127ACNG+ 0°C to +70°C 24 Narrow PDIP
+Denotes a lead(Pb)-free/RoHS-compliant package.
INL
(LSB)
±1/2
±1
Ordering Information continued at end of data sheet.
Features
●● 12-Bit Resolution, 1/2 LSB Linearity
●● +5V Single-Supply Operation
●● I2C-Compatible, 2-Wire Serial Interface
●● Four Software-Selectable Input Ranges
• MAX127: 0 to +10V, 0 to +5V, ±10V, ±5V
• MAX128: 0 to +VREF, 0 to +VREF/2, ±VREF,
±VREF/2
●● 8 Analog Input Channels
●● 8ksps Sampling Rate
●● ±16.5V Overvoltage-Tolerant Input Multiplexer
●● Internal 4.096V or External Reference
●● Two Power-Down Modes
●● 24-Pin Narrow PDIP or 28-Pin SSOP Packages
Typical Operating Circuit
+5V
0.1µF
ANALOG
INPUTS
4.7µF
VDD
SHDN
CH0
CH1
CH2
CH3 MAX127
CH4
CH5
MAX128
CH6
CH7
REF
REFADJ
SCL
SDA
A0
A1
A2
0.01µF
DGND AGND
µC
SCL SDA
1kΩ
Pin Configurations appear at end of data sheet.
19-4773; Rev 1; 12/12
1 page  
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7μF at REF; external clock, fCLK = 400kHz;
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
DIGITAL INPUTS (SDA, SCL)
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (SDA)
Output Low Voltage
Three-State Output Capacitance
SYMBOL
CONDITIONS
VIH
VIL
VHYS
IIN
CIN
VIN = 0V or VDD
(Note 4)
VOL
COUT
ISINK = 3mA
ISINK = 6mA
(Note 4)
MIN TYP MAX UNITS
0.7 x VDD
0.3 x VDD
0.05 x VDD
±0.1 ±10
15
V
V
V
µA
pF
0.4
V
0.6
15 pF
Timing Characteristics
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7μF at REF pin; TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
2-WIRE FAST MODE
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Receiving)
Fall Time for Both SDA and SCL
Signals (Transmitting)
Set-Up Time for STOP Condition
Capacitive Load for Each
Bus Line
Pulse Width of Spike Suppressed
SYMBOL
CONDITIONS
fSCL
tBUF
tHD,STA
tLOW
tHIGH
tSU,STA
tHD,DAT
tSU,DAT
tR Cb = Total capacitance of one bus line in pF
tF Cb = Total capacitance of one bus line in pF
tF Cb = Total capacitance of one bus line in pF
tSU,STO
Cb
tSP
MIN TYP
1.3
0.6
1.3
0.6
0.6
0
100
20 +
0.1 x Cb
20 +
0.1 x Cb
20 +
0.1 x Cb
0.6
0
MAX UNITS
400 kHz
µs
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
250 ns
µs
400 pF
50 ns
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address.
The first four bits (MSBs) of the slave address have been
factory programmed and are always 0101. The logic state
of the address input pins (A2–A0) determine the three
LSBs of the device address (Figure 3). A maximum of
eight MAX127/MAX128 devices can therefore be con-
nected on the same bus at one time.
A2–A0 may be connected to VDD or DGND, or they may
be actively driven by TTL or CMOS logic levels.
The eighth bit of the address byte determines whether the
master is writing to or reading from the MAX127/MAX128
(R/W = 0 selects a write condition. R/W = 1 selects a read
condition).
Conversion Control
The master signals the beginning of a transmission with
a START condition (S), which is a high-to-low transition
on SDA while SCL is high. When the master has finished
communicating with the slave, the master issues a STOP
condition (P), which is a low-to-high transition on SDA
while SCL is high (Figure 4). The bus is then free for
another transmission. Figure 5 shows the timing diagram
for signals on the 2-wire interface. The address-byte,
control-byte, and data-byte are transmitted between the
START and STOP conditions. The SDA state is allowed to
change only while SCL is low, except for the START and
STOP conditions. Data is transmitted in 8-bit words. Nine
clock cycles are required to transfer the data in or out of
the MAX127/MAX128. (Figures 9 and 10).
SLAVE ADDRESS
0
SDA
SCL
10
1 A2 A1 A0 R/W ACK
LSB
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS A2, A1, AND A0.
Figure 3. Address Byte
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. START and STOP Conditions
SDA
tLOW
tSU,DAT
tHD,DAT
SCL
tHD,STA
START CONDITION
tHIGH
tR tF
Figure 5. 2-Wire Serial-Interface Timing Diagram
tSU,STA
tHD,STA
REPEATED START CONDITION
tSU,STO
tBUF
STOP CONDITION START CONDITION
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX127.PDF ] | |
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