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PDF MAX125 Data sheet ( Hoja de datos )

Número de pieza MAX125
Descripción 2x4-Channel / Simultaneous-Sampling 14-Bit DAS
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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19-1319; Rev 2; 6/07
EVAALVUAAILTAIOBNLEKIT
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
General Description
The MAX125/MAX126 are high-speed, multichannel,
14-bit data-acquisition systems (DAS) with simultaneous
track/holds (T/Hs). These devices contain a 14-bit, 3µs,
successive-approximation analog-to-digital converter
(ADC), a +2.5V reference, a buffered reference input,
and a bank of four simultaneous-sampling T/H ampli-
fiers that preserve the relative phase information of the
sampled inputs. The MAX125/MAX126 have two multi-
plexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V; a fault condition on any channel will not harm
the IC. Available input ranges are ±5V (MAX125) and
±2.5V (MAX126).
An on-board sequencer converts one to four channels
per CONVST pulse. In the default mode, one T/H output
(CH1A) is converted. An interrupt signal (INT) is provided
after the last conversion is complete. Convert two,
three, or four channels by reprogramming the
MAX125/MAX126 through the bidirectional parallel
interface. Once programmed, the MAX125/MAX126
continue to convert the specified number of channels
per CONVST pulse until they are reprogrammed. The
channels are converted sequentially, beginning with
CH1. The INT signal always follows the end of the last
conversion in a conversion sequence. The ADC con-
verts each assigned channel in 3µs and stores the
result in an internal 14x4 RAM. Upon completion of the
conversions, data can be accessed by applying suc-
cessive pulses to the RD pin. Four successive reads
access four data words sequentially.
The parallel interface’s data-access and bus-release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microproces-
sors, so the MAX125/MAX126 conversion results can
be accessed without resorting to wait states.
Applications
Multiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring
Digital Signal Processing
Vibration and Waveform Analysis
Features
o Four Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (eight single-ended inputs
total)
o 3µs Conversion Time per Channel
o Throughput: 250ksps (1 channel)
142ksps (2 channels)
100ksps (3 channels)
76ksps (4 channels)
o Input Range: ±5V (MAX125)
±2.5V (MAX126)
o Fault-Protected Input Multiplexer (±17V)
o ±5V Supplies
o Internal +2.5V or External Reference Operation
o Programmable On-Board Sequencer
o High-Speed Parallel DSP Interface
Ordering Information
PART
TEMP RANGE
PIN-
INL
PACKAGE (LSB)
PKG
CODE
MAX125CCAX 0°C to +70°C 36 SSOP ±4 A36-4
MAX125CEAX -40°C to +85°C 36 SSOP ±4 A36-4
MAX126CCAX 0°C to +70°C 36 SSOP ±4 A36-4
MAX126CEAX -40°C to +85°C 36 SSOP ±4 A36-4
Typical Operating Circuit appears at end of data sheet.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX125 pdf
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
TIMING CHARACTERISTICS (Figure 4)
(AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONVST Pulse Width
CS to WR Setup Time
CS to WR Hold Time
WR Low Pulse Width
CS to CONVST Delay
Address Setup Time
Address Hold Time
RD to INT Delay
Delay Time Between Reads
CS to RD Setup Time
CS to RD Hold Time
RD Low Pulse Width
Data-Access Time
Bus-Relinquish Time
Conversion Time
Conversion Rate/Channel
Start-Up Time
SYMBOL
tCW
tCWS
tCWH
tWR
tCSD
tAS
tAH
tID
tRD
tCRS
tCRH
tRD
tDA
tDH
tCONV
CONDITIONS
25pF load
25pF load (Note 13)
25pF load (Note 14)
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Exiting shutdown
MIN TYP
30
0
0
30
125
30
0
40
0
0
30
5
5
MAX
30
30
45
3
6
9
12
250
142
100
76
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ksps
µs
Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 2: Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: CLK synchronized with CONVST.
Note 4: fIN = 10.06kHz, VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7: Guaranteed by design. Not production tested.
Note 8: AVDD = +5V, AVSS = -5V, DVDD = +5V, VIN = 0V (all channels).
Note 9: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as
TC = [REFOUT/REFOUT] / T.
Note 10: See Figure 2.
Note 11: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN = 2.5V (internal).
Note 12: Tested with VIN = AGND on all channels, VREFIN = 2.5V (internal).
Note 13: The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14: The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
_______________________________________________________________________________________ 5

5 Page





MAX125 arduino
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
OUTPUT CODE
TO DAC
MAX125
MAX126
REFOUT 7 (2.5V)
4.7µF
AV = 1
REFIN 6 (2.5V)
OUT
MAX6325
10k
2.5V
Figure 7. External Reference
1ppm/°C (max) temperature drift. Connect an external
reference at REFIN as shown in Figure 7. The minimum
impedance is 7kfor DC currents in both normal oper-
ation and shutdown. Bypass REFOUT with a 4.7µF low-
ESR capacitor.
Power-On Reset
When power is first applied, the internal power-on-reset
circuitry activates the MAX125/MAX126 with INT =
high, ready to convert. The default conversion mode is
Input Mux A/Single-Channel Conversion. See the
Programming Modes section if other configurations are
desired.
After the power supplies have been stabilized, the reset
time is 5µs; no conversions should be performed
during this phase. At power-up, data in memory is
undefined.
Software Power-Down
Software power-down is activated by setting bit A3 of
the control word high (Table 1). It is asserted after the
WR or CS rising edge, at which point the ADC immedi-
ately powers down to a low quiescent-current state.
AVDD drops to less than 1.5mA, and AVSS is reduced
to less than 1mA. The ADC blocks and reference buffer
are turned off, but the digital interface and the refer-
ence remain active for fast power-up recovery. Wake
up the MAX125/MAX126 by writing a control word
(A0–A3, Table 1). The bidirectional interface interprets
a logic zero at A3 as the start signal and powers up in
the mode selected by A0, A1, and A2. The reference
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
1LSB = 4VREFOUT
16384
100 . . . 001
100 . . . 000
- FS ZERO
INPUT VOLTAGE (LSB)
FS = 2 x VREFOUT (MAX125)
FS = VREFOUT (MAX126)
Figure 8. Bipolar Transfer Function
+FS - 1LSB
buffer’s settling time and the bypass capacitor’s value
dominate the power-up delay. With the recommended
4.7µF at REFOUT, the power-up delay is typically 5µs.
Transfer Function
The MAX125/MAX126 have bipolar input ranges. Fig-
ure 8 shows the bipolar/output transfer function. Code
transitions occur at successive-integer least significant
bit (LSB) values. Output coding is twos-complement
binary with 1LSB = 610µV for the MAX125 and
1LSB = 305µV for the MAX126.
Output Demultiplexer
An output demultiplexer circuit is useful for isolating
data from one channel in a four-channel conversion
sequence. Figure 9’s circuit uses the external 16MHz
clock and the INT signal to generate four RD pulses
and a latch clock to save data from the desired chan-
nel. CS must be low during the four RD pulses. The
channel is selected with the binary coding of two
switches. A 16-bit 16373 latch simplifies layout.
Motor-Control Applications
Vector motor control requires monitoring of the individ-
ual phase currents. In their most basic application, the
MAX125/MAX126 simultaneously sample two currents
(CH1A and CH2A, Figure 10) and preserve the neces-
sary relative phase information. Only two of the three
phase currents have to be digitized, because the third
component can be mathematically derived with a coor-
dinate transformation.
______________________________________________________________________________________ 11

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