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PDF MAX1248 Data sheet ( Hoja de datos )
| Número de pieza | MAX1248 | |
| Descripción | 2x4-Channel / Simultaneous-Sampling 14-Bit DAS | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1248 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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19-1072; Rev 2; 5/98
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________General Description
The MAX1248/MAX1249 10-bit data-acquisition sys-
tems combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from
a single +2.7V to +5.25V supply, and their analog
inputs are software configurable for unipolar/bipolar
and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection
to TMS320-family digital signal processors. The
MAX1248/MAX1249 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions.
The MAX1248 has an internal 2.5V reference, while the
MAX1249 requires an external reference. Both parts
have a reference-buffer amplifier with a ±1.5% voltage
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX1248/MAX1249, and the quick
turn-on time allows them to be shut down between all
conversions. This technique can cut supply current to
under 60µA at reduced sampling rates.
The MAX1248/MAX1249 are available in a 16-pin DIP
and a very small QSOP that occupies the same board
area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX148/MAX149 data sheet.
____________________________Features
o 4-Channel Single-Ended or 2-Channel
Differential Inputs
o Single +2.7V to +5.25V Operation
o Internal 2.5V Reference (MAX1248)
o Low Power: 1.2mA (133ksps, +3V supply)
54µA (1ksps, +3V supply)
1µA (power-down mode)
o SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
o Software-Configurable Unipolar or Bipolar Inputs
o 16-Pin QSOP Package (same area as 8-pin SO)
_____________Ordering Information
PART†
TEMP. RANGE
PIN-PACKAGE
INL
(LSB)
MAX1248ACPE
MAX1248BCPE
MAX1248ACEE
MAX1248BCEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
16 QSOP
±1/2
±1
±1/2
±1
Ordering Information continued at end of data sheet.
†Contact factory for availability of alternate surface-mount
packages.
________________________Applications __________Typical Operating Circuit
Portable Data Logging
Medical Instruments
Pen Digitizers
Data Acquisition
Battery-Powered Instruments
System Supervision
Pin Configuration appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
0V TO
+2.5V
ANALOG
INPUTS
C1
4.7µF
C2
0.01µF
CH0 VDD
DGND
MAX1248 AGND
CH3 COM
CS
SCLK
VREF DIN
DOUT
SSTRB
REFADJ
SHDN
+3V
VDD
C3
0.1µF
CPU
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
1 page  
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SYMBOL
CONDITIONS
tACQ
tDS
tDH
tDO
Figure 1
MAX124_ _C/E
MAX124_ _M
tDV Figure 1
tTR Figure 2
tCSS
tCSH
tCH
tCL
tSSTRB
Figure 1
tSDV External clock mode only, Figure 1
tSTR External clock mode only, Figure 2
tSCK Internal clock mode only (Note 10)
MIN TYP MAX UNITS
1.5 µs
100 ns
0 ns
20 200
ns
20 240
240 ns
240 ns
100 ns
0 ns
200 ns
200 ns
240 ns
240 ns
240 ns
0 ns
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7 Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10 Guaranteed by design. Not subject to production testing.
Note 11: The MAX1249 typically draws 400µA less than the values shown.
Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
_______________________________________________________________________________________ 5
5 Page 
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
CS
SCLK
1
tACQ
48
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
START
RB1
A/D STATE
ACQUISITION
IDLE 1.5µs
(fCLK = 2MHz)
12 16
20 24
RB2 RB3
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
FILLED WITH
S0 ZEROS
CONVERSION
IDLE
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK ≤ 2MHz)
CS
SCLK
DIN
DOUT
tCSS
tCSH
tDS
tDH
tDV
•••
tCH
tCL
•••
•••
•••
tCSH
tDO tTR
Figure 6. Detailed Serial-Interface Timing
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MAX1248.PDF ] | |
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