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PDF MAX1198 Data sheet ( Hoja de datos )
| Número de pieza | MAX1198 | |
| Descripción | Dual / 8-Bit / 100Msps / 3.3V / Low-Power ADC with Internal Reference and Parallel Outputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2412; Rev 0; 4/02
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1198 is a 3.3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1198
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
264mW, while delivering a typical signal-to-noise and
distortion (SINAD) of 48.1dB at an input frequency of
50MHz and a sampling rate of 100Msps. The T/H-driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1198 features a 3.2mA sleep mode, as well as a
0.15µA power-down mode to conserve power during
idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1198 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1198 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1198
are also available. Refer to the MAX1195 data sheet for
40Msps and the MAX1197 data sheet for 60Msps. In
addition to these speed grades, this family includes a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1180 data sheet. With the N.C. pins of the
MAX1198 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1180.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical
Imaging
Battery-Powered
Instrumentation
WLAN, WWAN, WLL,
MMDS Modems
Set-Top Boxes
VSAT Terminals
Features
o Single 2.7V to 3.6V Operation
o Excellent Dynamic Performance
48.1dB/47.6dB SINAD at fIN = 50MHz/200MHz
66dBc/61.5dBc SFDR at fIN = 50MHz/200MHz
o -72dB Interchannel Crosstalk at fIN = 50MHz
o Low Power
264mW (Normal Operation)
10.6mW (Sleep Mode)
0.5µW (Shutdown Mode)
o 0.05dB Gain and ±0.1° Phase Matching
o Wide ±1VP-P Differential Analog Input Voltage
Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
Ordering Information
PART
MAX1198ECM
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
*EP = Exposed paddle
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1198
TQFP-EP
36 N.C.
35 N.C.
34 OGND
33 OVDD
32 OVDD
31 OGND
30 N.C.
29 N.C.
28 D0B
27 D1B
26 D2B
25 D3B
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Low Threshold
CLK
VIL
PD, OE, SLEEP, T/B
0.2 ×
VDD
0.2 ×
OVDD
V
Input Hysteresis
VHYST
Input Leakage
IIH
IIL
Input Capacitance
CIN
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
VIH = VDD = OVDD
VIL = 0
0.15
±20
±20
5
V
µA
pF
Output Voltage Low
VOL ISINK = -200µA
0.2 V
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
VOH
ILEAK
COUT
ISOURCE = 200µA
OE = OVDD
OE = OVDD
OVDD -
0.2
V
±10 µA
5 pF
Analog Supply Voltage Range
Output Supply Voltage Range
VDD
OVDD
CL = 15pF
2.7 3.3 3.6
1.7 2.5 3.6
V
V
Analog Supply Current
IVDD
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
80 95
3.2
0.15 20
mA
µA
Output Supply Current
IOVDD
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels (Note 6)
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
11.5
2
2 10
mA
µA
Analog Power Dissipation
Power-Supply Rejection
TIMING CHARACTERISTICS
PDISS
PSRR
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset, VDD ±5%
Gain, VDD ±5%
264 314
mW
10.6
0.5 66 µW
±3
mV/V
±3
CLK Rise to Output Data Valid
Time
tDO CL = 20pF (Notes 1, 7)
6 8.25 ns
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
tENABLE
tDISABLE
tCH
tCL
Clock period: 10ns (Note 7)
Clock period: 10ns (Note 7)
5
5
5 ±0.5
5 ±0.5
ns
ns
ns
ns
_______________________________________________________________________________________ 5
5 Page 
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description (continued)
PIN NAME
FUNCTION
42
D5A
Three-State Digital Output, Bit 5, Channel A
43
D6A
Three-State Digital Output, Bit 6, Channel A
44
D7A
Three-State Digital Output, Bit 7 (MSB), Channel A
45 REFOUT Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-
divider.
46
REFIN
Reference Input. VREFIN = 2 x (VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.
47
REFP
Positive Reference I/O. Conversion range is ±(VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.
48
REFN
Negative Reference I/O. Conversion range is ±(VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.
STAGE 1
STAGE 2
STAGE 6
2-BIT FLASH
ADC
STAGE 7
STAGE 1
STAGE 2
STAGE 6
2-BIT FLASH
ADC
STAGE 7
DIGITAL ALIGNMENT LOGIC
T/H 8
DIGITAL ALIGNMENT LOGIC
T/H 8
VINA D7A–D0A
VINB D7B–D0B
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
Detailed Description
The MAX1198 uses a seven-stage, fully differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been processed
by all seven stages.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX1198.PDF ] | |
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