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PDF MAX1190 Data sheet ( Hoja de datos )
| Número de pieza | MAX1190 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2524; Rev 1; 6/06
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1190 is a 3.3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1190 is
optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumentation,
and digital communications. This ADC operates from a
single 3.1V to 3.6V supply, consuming only 492mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 57dB at an input frequency of 60MHz and a sampling
rate of 120Msps. The T/H driven input stages incorporate
400MHz (-3dB) input amplifiers. The converters can also
be operated with single-ended inputs. In addition to low
operating power, the MAX1190 features a 3mA sleep
mode, as well as a 1µA power-down mode to conserve
power during idle periods.
An internal 2.048V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure
allows the use of this internal or an externally applied ref-
erence, if desired, for applications requiring increased
accuracy or a different input voltage range.
The MAX1190 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1190 is available in a 7mm ✕
7mm, 48-pin TQFP-EP package, and is specified for the
extended industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1190 are
also available. Refer to the MAX1180–MAX1184 data
sheets for 105Msps/80Msps/65Msps/40Msps. In addition
to these speed grades, this family includes two multi-
plexed output versions (MAX1185/MAX1186 for
20Msps/40Msps), for which digital data is presented time-
interleaved and on a single, parallel 10-bit output port.
For lower speed, pin-compatible, 8-bit versions of the
MAX1190, refer to the MAX1195–MAX1198 data sheets.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Functional Diagram appears at end of data sheet.
Features
♦ Single 3.3V Operation
♦ Excellent Dynamic Performance
57dB SINAD at fIN = 60MHz
64dBc SFDR at fIN = 60MHz
♦ -71dBc Interchannel Crosstalk at fIN = 60MHz
♦ Low Power
492mW (Normal Operation)
10mW (Sleep Mode)
3.3µW (Shutdown Mode)
♦ 0.08dB Gain and 0.8° Phase Matching
♦ Wide ±1VP-P Differential Analog Input Voltage
Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s Complement
or Offset Binary
♦ Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit
Versions Available
Ordering Information
PART
TEMP RANGE PIN-PACKAGE PKG CODE
MAX1190ECM -40°C to +85°C 48 TQFP-EP*
C48E-7
MAX1190ECM+ -40°C to +85°C 48 TQFP-EP*
C48E-7
*EP = Exposed paddle.
+Denotes lead-free package.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
EP
MAX1190
36 D1A
35 D0A
34 OGND
33 OVDD
32 OVDD
31 OGND
30 D0B
29 D1B
28 D2B
27 D3B
26 D4B
25 D5B
EP = EXPOSED PADDLE.
TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A “+”.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA =
TMIN to TMAX, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at TA = +25°C.)
PARAMETER
Analog Supply Current
Output Supply Current
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
IVDD
Operating, fINA and B = 20.01MHz at
-0.5dBFS
Sleep mode
149 185
3
mA
Shutdown, clock idle, PD = OE = OVDD
1 15 µA
IOVDD
Operating, fINA and B = 20.01MHz at -0.5dBFS;
see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
16
mA
Analog Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse-Width High
CLK Pulse-Width Low
Wake-Up Time
PDISS
PSRR
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA and B = 20.01MHz at
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset, VDD ±5%
Gain, VDD ±5%
tDO
tENABLE
tDISABLE
tCH
tCL
tWAKE
CL = 20pF (Note 3)
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
Wake up from sleep mode (Note 4)
Wake up from shutdown mode (Note 4)
100
2
492
10
3.3
±3.4
±0.81
10
611
50
µA
mW
µW
mV/V
%/V
4.8 7.4
4.7
1.2
4.17
ns
ns
ns
ns
4.17 ns
0.65
µs
1.2
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
fINA or B = 20.01MHz at -0.5dBFS
fINA or B = 20.01MHz at -0.5dBFS (Note 5)
fINA or B = 20.01MHz at -0.5dBFS (Note 6)
-71 dBc
0.08 ±0.2
dB
0.8 Degrees
Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
_______________________________________________________________________________________ 5
5 Page 
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description (continued)
PIN NAME
FUNCTION
40 D5A Three-State Digital Output, Bit 5, Channel A
41 D6A Three-State Digital Output, Bit 6, Channel A
42 D7A Three-State Digital Output, Bit 7, Channel A
43 D8A Three-State Digital Output, Bit 8, Channel A
44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A
45 REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.
46 REFIN Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor.
47 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor.
48 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor.
— EP Exposed Paddle. Connect to analog ground.
Detailed Description
The MAX1190 uses a nine-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by 2, and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages.
Input Track-and-Hold Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuits sample the input
signals onto the two capacitors (C2a and C2b) through
switches S4a and S4b. S2a and S2b set the common
mode for the amplifier input, and open simultaneously
with S1, sampling the input waveform. Switches S4a,
S4b, S5a, and S5b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier and switch S4c is closed. The
resulting differential voltages are held on capacitors
C2a and C2b. The amplifiers are used to charge capac-
itors C1a and C1b to the same values originally held on
C2a and C2b.
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
T/H
VINA
DIGITAL ALIGNMENT LOGIC
10
DIGITAL ALIGNMENT LOGIC
T/H 10
D9A–D0A
VINB
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
D9B–D0B
Figure 1. Pipelined Architecture—Stage Blocks
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX1190.PDF ] | |
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