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PDF MAX1183 Data sheet ( Hoja de datos )
| Número de pieza | MAX1183 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated | |
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19-2173; Rev 1; 7/06
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
General Description
The MAX1183 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1183 is optimized for low-power, high
dynamic performance applications in imaging, instrumen-
tation, and digital communication applications. This ADC
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a typical signal-to-noise ratio
(SNR) of 59.6dB at an input frequency of 20MHz and a
sampling rate of 40Msps. The T/H driven input stages
incorporate 400MHz (-3dB) input amplifiers. The convert-
ers may also be operated with single-ended inputs. In
addition to low operating power, the MAX1183 features a
2.8mA sleep mode as well as a 1µA power-down mode to
conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1183 features parallel, CMOS-compatible
three-state outputs. The digital output format can be set
to two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1183 is available in a 7mm ✕ 7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower and higher speed versions of the
MAX1183 are also available. See Table 2 at end of data
sheet for a list of pin-compatible versions. Refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
and the MAX1184 data sheet for 20Msps. In addition to
these speed grades, this family includes a multiplexed
output version, for which digital data is presented time-
interleaved and on a single, parallel 10-bit output port.
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
Features
♦ Single 3V Operation
♦ Excellent Dynamic Performance:
59.6dB SNR at fIN = 20MHz
73dB SFDR at fIN = 20MHz
♦ Low Power:
40mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦ 0.02dB Gain and 0.25° Phase Matching
♦ Wide ±1VP-P Differential Analog Input Voltage
Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s
Complement or Offset Binary
♦ 48-Pin TQFP Package with Exposed Paddle for
Improved Thermal Dissipation
Ordering Information
PART
MAX1183ECM
MAX1183ECM+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
48 TQFP-EP*
*EP = Exposed paddle.
+Denotes lead-free package.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
MAX1183
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
EP
36 D1A
35 D0A
34 OGND
33 OVDD
32 OVDD
31 OGND
30 D0B
29 D1B
28 D2B
27 D3B
26 D4B
25 D5B
Functional Diagram appears at end of data sheet.
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A “+” SIGN.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLK Pulse Width High
tCH Figure 3, clock period: 25ns
12.5
±3.8
ns
CLK Pulse Width Low
tCL Figure 3, clock period: 25ns
12.5
±3.8
ns
Wake-Up Time
tWAKE
Wake up from sleep mode (Note 6)
Wake up from shutdown (Note 6)
0.41
µs
1.5
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
-70 dB
0.02 ±0.2
dB
0.25 Degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Typical Operating Characteristics
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL ≈ 10pF, TA = +25°C, unless
otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10
CHA
fCLK = 40.0006MHz
fINA = 7.5343MHz
-20 fINB = 6.1475MHz
-30 AINA = -0.498dBFS
-40
-50
-60 HD3
-70
HD2
-80
-90
-100
0
2 4 6 8 10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10 CHB
-20
-30
fCLK = 40.0006MHz
fINB = 6.1475MHz
fINA = 7.5343MHz
AINB = -0.534dBFS
-40
-50
-60 HD3
-70 HD2
-80
-90
-100
0
2 4 6 8 10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10
fCLK = 40.0006MHz
fINA = 24.9662MHz
-20 fINB = 19.888MHz
AINA = -0.552dBFS
-30
CHA
-40
-50
-60 HD3
-70 HD2
-80
-90
-100
0
2 4 6 8 10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________ 5
5 Page 
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switch-
es S3a and S3b connect capacitors C1a and C1b to
the output of the amplifier and switch S4c is closed.
The resulting differential voltages are held on capaci-
tors C2a and C2b. The amplifiers are used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. These values are then presented
to the first-stage quantizers and isolate the pipelines
from the fast-changing inputs. The wide input bandwidth
T/H amplifiers allow the MAX1183 to track-and-sam-
ple/hold analog inputs of high frequencies (> Nyquist).
INTERNAL
BIAS
S2a
S4a
INA+
C2a
S4c S1
COM
S5a
C1a S3a
OUT
INA-
S4b
C2b
OUT
C1b
S2b
INTERNAL
BIAS
INTERNAL
BIAS
S2a
S3b
S5b
COM
COM
S5a
C1a S3a
HOLD
HOLD
CLK
TRACK
TRACK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
S4a
INB+
C2a
S4c S1
OUT
INB-
S4b
C2b
OUT
MAX1183
C1b
S2b
INTERNAL
BIAS
S3b
S5b
COM
Figure 2. MAX1183 T/H Amplifiers
The ADC inputs (INA+, INB+, INA- and INB-) can be
driven either differentially or single-ended. Match the
impedance of INA+ and INA-, as well as INB+ and INB-
and set the common-mode voltage to midsupply
(VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1183 is determined by
the internally generated voltage difference between
REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 -
VREFIN/4). The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.
The MAX1183 provides three modes of reference
operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.
Clock Input (CLK)
The MAX1183’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
SNR
=
20
×
log
⎛
⎝⎜
2
×
π
×
1
fIN
×
tAJ
⎞
⎠⎟
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1183.PDF ] | |
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