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PDF MAX1180 Data sheet ( Hoja de datos )
| Número de pieza | MAX1180 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated | |
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19-2097; Rev 1; 2/07
EVAALVUAAILTAIOBNLEKIT
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1180 is a 3.3V, dual 10-bit, analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, nine-
stage ADCs. The MAX1180 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation, and digital communication applica-
tions. The MAX1180 operates from a single 2.7V to 3.6V
supply, consuming only 413mW, while delivering a typi-
cal signal-to-noise ratio (SNR) of 58.5dB at an input fre-
quency of 20MHz and a sampling rate of 105Msps. The
T/H driven input stages incorporate 400MHz (-3dB)
input amplifiers. The converters may also be operated
with single-ended inputs. In addition to low operating
power, the MAX1180 features a 2.8mA sleep mode, as
well as a 1µA power-down mode to conserve power
during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or external
reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1180 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1180 is available in a 7mm ✕ 7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1180 are also available. Please refer to the
MAX1181 data sheet for 80Msps, the MAX1182 data
sheet for 65Msps, the MAX1183 data sheet for 40Msps,
and the MAX1184 data sheet for 20Msps. In addition to
these speed grades, this family includes a 20Msps mul-
tiplexed output version (MAX1185), for which digital
data is presented time-interleaved on a single, parallel
10-bit output port.
Applications
High Resolution Imaging
I/Q Channel Digitization
Multichannel IF Undersampling
Instrumentation
Video Application
Features
♦ Single 3.3V Operation
♦ Excellent Dynamic Performance
58.5dB SNR at fIN = 20MHz
72dB SFDR at fIN = 20MHz
♦ SNR Flat within 1dB for fIN = 20MHz to 100MHz
♦ Low Power
125mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦ 0.02dB Gain and 0.25° Phase Matching (typ)
♦ Wide ±1VP-P Differential Analog Input Voltage
Range
♦ 400MHz, -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s
Complement or Offset Binary
♦ 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX1180ECM
-40°C to +85°C 48 TQFP-EP*
MAX1180ECM+
-40°C to +85°C 48 TQFP-EP*
+Denotes a lead-free and RoHS-compliant package.
*EP = Exposed paddle.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1180
EP
36 D1A
35 D0A
34 OGND
33 OVDD
32 OVDD
31 OGND
30 D0B
29 D1B
28 D2B
27 D3B
26 D4B
25 D5B
Functional Diagram appears at end of data sheet.
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED
BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 105.263MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse-Width High
IOVDD
PDISS
PSRR
Operating, CL = 15pF , fINA or B = 20MHz at
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA or B = 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
tDO
tENABLE
tDISABLE
Figure 3 (Note 5)
Figure 4
Figure 4
tCH Figure 3, clock period: 9.5ns
15 mA
100
2 10
µA
413 511 mW
9.2
µW
3 50
±0.2 mV/V
±0.1 %/V
58
10
1.5
4.75
±1.5
ns
ns
ns
ns
CLK Pulse-Width Low
tCL Figure 3, clock period: 9.5ns
4.75
±1.5
ns
Wake-Up Time (Note 6)
tWAKE
Wakeup from sleep mode
Wakeup from shutdown
0.18
µs
1.5
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
-70
0.02 ±0.2
dB
dB
Phase Matching
fINA or B = 20MHz at -0.5dBFS
0.25 degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________ 5
5 Page 
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
VIN T/H Σ x2 VOUT
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
DIGITAL CORRECTION LOGIC
T/H 10
DIGITAL CORRECTION LOGIC
T/H 10
VINA D9A–D0A
VINB D9B–D0B
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
Detailed Description
The MAX1180 uses a nine-stage, fully-differential
pipelined architecture (Figure 1), that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (two-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held-input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a and S5b are closed. The fully-differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a and S4b are then opened before
switches S3a and S3b, connect capacitors C1a and
C1b to the output of the amplifier, and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1180 to track-
and-sample/hold analog inputs of high frequencies
(> Nyquist). Both ADC inputs (INA+, INB+, INA-, and
INB-) can be driven either differentially or single-ended.
Match the impedance of INA+ and INA-, as well as
INB+ and INB-, and set the common-mode voltage to
midsupply (VDD / 2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1180 is determined
by the internally generated voltage difference
between REFP (VDD / 2 + VREFIN / 4) and REFN (VDD / 2 -
VREFIN / 4).The full-scale range for both on-chip
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX1180.PDF ] | |
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