|
|
PDF MAX1151 Data sheet ( Hoja de datos )
| Número de pieza | MAX1151 | |
| Descripción | 750Msps Flash ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX1151 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
19-1170; Rev 0; 12/96
EVAALVUAAILTAIOBNLEKIT
8-Bit, 750Msps Flash ADC
_______________General Description
The MAX1151 is a parallel flash analog-to-digital con-
verter (ADC) capable of digitizing full-scale (0V to -2V)
inputs into 8-bit digital words at an update rate of
750Msps. The ECL-compatible outputs are demuxed
into two separate output banks, each with differential
data-ready outputs to ease the task of data capture.
The MAX1151’s wide input bandwidth and low capaci-
tance eliminate the need for external track/hold amplifi-
ers for most applications. A proprietary decoding
scheme reduces metastable errors to 1LSB. This device
operates from a single -5.2V supply, with a nominal
power dissipation of 5.5W.
______________Ordering Information
PART
MAX1151AIZS
MAX1151BIZS
TEMP. RANGE
-20°C to +85°C
-20°C to +85°C
PIN-PACKAGE
80 MQUAD
80 MQUAD
____________________________Features
o 1:2 Demuxed ECL-Compatible Outputs
o Wide Input Bandwidth: 900MHz
o Low Input Capacitance: 15pF
o Metastable Errors Reduced to 1LSB
o Single -5.2V Supply
________________________Applications
Digital Oscilloscopes
Data Acquisition
Transient-Capture Applications
Radar, EW, ECM
Direct RF/IF Downconversion
Pin Configuration appears on last page.
_________________________________________________________Functional Diagram
CLK NCLK
ANALOG
VRT INPUT
PREAMP COMPARATOR
255
CLOCK
BUFFER
DEMUX
CLOCK BUFFER
MAX1151
VRM
VFB
254
D8
(OVR)
152
D7
(MSB)
151
D6
128 D5
127
D4
64
D3
63
D2
2
D1
1
D0
(LSB)
D8B
D7B
•
•
D5B
•
•
D2B
D1B
D0B
D8A
D7A
•
•
•
D5A
•
•
•
D2A
D1A
D0A
NDRB (NOT DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
NDRA (NOT DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
BANK B
BANK A
________________________________________________________________ Maxim Integrated Products 1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
8-Bit, 750Msps Flash ADC
The MAX1151 has true differential analog and digital
data paths from the preamplifiers to the output buffers
(current-mode logic) for reducing potential missing
codes while rejecting common-mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The device’s output drive capability can
provide full ECL swings into 50Ω loads.
Typical Interface Circuit
The circuit of Figure 1 shows a method of achieving the
least error by correcting for integral linearity, input-
induced distortion, and power-supply/ground noise. This
is achieved with the use of external reference-ladder tap
connections, an input buffer, and supply decoupling.
Contact the factory for the MAX1150/MAX1151 evalua-
tion kit manual, which contains more details on interfac-
ing the MAX1151. The function of each pin and external
connections to other components are described in the fol-
lowing sections.
VEE, AGND, DGND
VEE is the supply pin with AGND as ground for the
device. The power-supply pins should be bypassed as
close to the device as possible with at least a 0.01µF
ceramic capacitor. A 1µF tantalum can also be used for
low-frequency suppression. DGND is the ground for the
ECL outputs, and should be referenced to the output
pulldown voltage and appropriately bypassed, as shown
in Figure 1.
VIN (Analog Input)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog
input sense, while the other is used for input force. This is
convenient for testing the source signal to see if there is
sufficient drive capability. The pins can also be tied to-
gether and driven by the same source. The MAX1151 is
superior to similar devices due to a preamplifier stage
before the comparators. This makes the device easier to
drive because it has constant capacitance and induces
less slew-rate distortion.
CLK, NCLK (Clock Inputs)
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be
kept at 50%, to avoid causing larger second harmonics.
If this is not important to the intended application, duty
cycles other than 50% may be used.
D0 to D8, DR, NDR (A and B)
The digital outputs can drive 50Ω to ECL levels when
pulled down to -2V. When pulled down to -5.2V, the out-
puts can drive 130Ω to 1kΩ loads. All digital outputs are
gray code, with the coding as shown in Table 1.
Table 1. Output Coding
VIN (V)
0
D8
1
-0.5 0
-1.0 0
-1.5 0
-2.0 0
D7 . . . D0
10000000
10000001
10000011
•
•
•
10100001
10100000
11100000
•
•
•
11000001
11000000
01000000
•
•
•
01100001
01100000
00100000
•
•
•
00000011
00000001
00000000
VRBF, VRBS, VRTF, VRTS, VRM
(Reference Inputs)
There are two reference inputs and one external refer-
ence voltage tap. These are -2V (VRB force and sense),
mid-tap (VRM), and AGND (VRT force and sense). The
reference pins and tap can be driven by op amps (as
shown in Figure 1), or VRM can be bypassed for limited
temperature operation. These voltage inputs can be by-
passed to AGND for further noise suppression, if
desired.
Thermal Management
The typical thermal impedance (θCA) for the MQUAD
package has been measured at θCA = 17°C/W, in still
air with no heatsink.
To ensure rated performance, we highly recommend
using this device with a heatsink that can provide ade-
quate air flow. We have found that a Thermalloy 17846
heatsink with a minimum air flow of 1 meter/second
(200 linear feet per minute) provides adequate thermal
performance under laboratory tests. Application-specif-
ic conditions should be taken into account to ensure
that the device is properly heat sinked.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX1151.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX115 | 2x4-Channel / Simultaneous-Sampling 12-Bit ADCs | Maxim Integrated |
| MAX1150 | 8-Bit / 500Msps Flash ADC | Maxim Integrated |
| MAX11500 | High-Definition Video Filter | Maxim Integrated |
| MAX11504 | Standard-Definition Video Filter |  Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |