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PDF MAX114 Data sheet ( Hoja de datos )

Número de pieza MAX114
Descripción +5V / 1Msps / 4 & 8-Channel / 8-Bit ADCs with 1A Power-Down
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX114 Hoja de datos, Descripción, Manual

19-1083; Rev 1; 8/96
+5V, 1Msps, 4 & 8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________General Description ____________________________Features
The MAX114/MAX118 are microprocessor-compatible,
8-bit, 4-channel and 8-channel analog-to-digital con-
verters (ADCs). They operate from a single +5V supply
and use a half-flash technique to achieve a 660ns con-
version time (1Msps). A power-down (PWRDN) pin
reduces current consumption typically to 1µA. The
devices return from power-down mode to normal oper-
ating mode in less than 200ns, allowing large supply-
current reductions in burst-mode applications (in burst
mode, the ADC wakes up from a low-power state at
specified intervals to sample the analog input signals).
Both converters include a track/hold, enabling the ADC
to digitize fast analog signals.
Microprocessor (µP) interfaces are simplified because the
ADC can appear as a memory location or I/O port without
external interface logic. The data outputs use latched,
three-state buffer circuitry for direct connection to an 8-bit
parallel µP data bus or system input port. The
MAX114/MAX118 input/reference configuration enables
ratiometric operation.
o Single +5V Supply Operation
o 4 (MAX114) or 8 (MAX118) Analog Input Channels
o Low Power: 40mW (operating mode)
5µW (power-down mode)
o Total Unadjusted Error 1LSB
o Fast Conversion Time: 660ns per Channel
o No External Clock Required
o Internal Track/Hold
o 1MHz Full-Power Bandwidth
o Internally Connected 8th Channel Monitors
Reference Voltage (MAX118)
______________Ordering Information
PART
MAX114CNG
MAX114CAG
TEMP. RANGE
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
24 Narrow Plastic DIP
24 SSOP
The 4-channel MAX114 is available in a 24-pin DIP or
SSOP. The 8-channel MAX118 is available in a 28-pin
DIP or SSOP. For +3V applications, refer to the
MAX113/MAX117 data sheet.
MAX114C/D
MAX114ENG
MAX114EAG
MAX114MRG
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
Dice*
24 Narrow Plastic DIP
24 SSOP
24 Narrow CERDIP**
________________________Applications Ordering Information continued on last page.
High-Speed DSP
Remote Data Acquisition
*Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability.
Portable Equipment Communications Systems
Pin Configurations appear on last page.
_________________________________________________________Functional Diagram
REF+
*IN8
*IN7
*IN6
*IN5
IN4
IN3
IN2
IN1
MUX
Σ
* MAX118 ONLY
ADDRESS
LATCH
DECODE
A0 A1 A2
4-BIT
FLASH
ADC
(4MSBs)
D7
D6
D5
D4
4-BIT
DAC
REF+
16
4-BIT
FLASH
ADC
(4LSBs)
THREE-
STATE
OUTPUT
DRIVERS
TIMING AND
CONTROL
MAX114/MAX118
REF- PWRDN RD
CS
MODE INT WR/RDY
D3
D2
D1
D0
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

1 page




MAX114 pdf
+5V, 1Msps, 4 & 8-Channel,
8-Bit ADCs with 1µA Power-Down
__________________________________________Typical Operating Characteristics
(VDD = +5V, TA = +25°C, unless otherwise noted.)
CONVERSION TIME
vs. AMBIENT TEMPERATURE
1.5
1.4
1.3
1.2
1.1 VDD = +4.75V
1.0
0.9
VDD = +5.25V
0.8
0.7 VDD = +5V
0.6
-60
-20 20 60 100
TEMPERATURE (°C)
140
EFFECTIVE NUMBER OF BITS vs.
INPUT FREQUENCY (WR-RD MODE)
8.0
7.5
7.0
6.5
fSAMPLE = 1MHz
VIN = 4.96Vp-p
6.0
1k
10k 100k
1M
INPUT FREQUENCY (Hz)
AVERAGE POWER CONSUMPTION
vs. SAMPLING RATE USING PWRDN
50
40
30
20
SIGNAL-TO-NOISE RATIO
0
VDD = 4.75V
-20 INPUT FREQUENCY =
195.8ksps
VIN = 4.72Vp-p
-40 SAMPLE
FREQUENCY = 1MHz
-60 SNR = 48.2dB
10 -80
0
1k 10k 100k 1M
SAMPLING RATE (CONVERSIONS/SEC)
-100
0
100 200 300 400
FREQUENCY (kHz)
500
TOTAL UNADJUSTED ERROR
vs. POWER-UP TIME
6
5
4
3
2
1
0
75
100 125 150 175 200 225 250
POWER-UP TIME, tUP (ns)
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDING REFERENCE CURRENT)
12
10
8
6
4
2
0
-60
-20 20 60 100
TEMPERATURE (°C)
140
_______________________________________________________________________________________ 5

5 Page





MAX114 arduino
+5V, 1Msps, 4 & 8-Channel,
8-Bit ADCs with 1µA Power-Down
Transfer Function
Figure 10 shows the MAX114/MAX118’s nominal trans-
fer function. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary
with 1LSB = (VREF+ - VREF-) / 256.
Conversion Rate
The maximum sampling rate (fMAX) for the MAX114/
MAX118 is achieved in write-read mode (tRD < tINTL),
and is calculated as follows:
fMAX = t WR
+
tRD
1
+
tRI
+
t ACQ
fMAX
=
250ns
+
250ns
1
+
150ns
+
160ns
fMAX = 1.23MHz
where tWR = the write pulse width, tRD = the delay
between write and read pulses, tRI = RD to INT delay,
and tACQ = minimum acquisition time.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit-
ed to frequencies above DC and below one-half the
ADC sample rate.
The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per-
fect 8-bit ADC can do no better than 50dB.
The FFT Plot (see Typical Operating Characteristics)
shows the result of sampling a pure 195.8kHz sinusoid
at a 1MHz rate. This FFT plot of the output shows the
output level in various spectral bands.
The effective resolution (or “effective number of bits”)
the ADC provides can be measured by transposing the
equation that converts resolution to SNR: N = (SINAD -
1.76) / 6.02 (see Typical Operating Characteristics).
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequency
OUTPUT CODE
11111111
11111110
11111101
FULL-SCALE
TRANSITION
1LSB = VREF+ - VREF-
256
00000011
00000010
00000001
00000000
VREF-
123
INPUT VOLTAGE (LSBs)
Figure 10. Transfer Function
FS
FS - 1LSB
VREF+
band above DC and below one-half the sample rate) to
the fundamental itself. This is expressed as:
THD = 20log

V2 2
+ V32
+ V42
+ ...VN2
V1

where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through Nth
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the amplitude of the
next largest spectral component (in the frequency
band above DC and below one-half the sample rate).
Usually the next largest spectral component occurs at
some harmonic of the input frequency. However, if the
ADC is exceptionally linear, it may occur only at a ran-
dom peak in the ADC’s noise floor. See the Signal-to-
Noise Ratio graph in Typical Operating Characteristics.
______________________________________________________________________________________ 11

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