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PDF M93C06 Data sheet ( Hoja de datos )

Número de pieza M93C06
Descripción 16Kbit / 8Kbit / 4Kbit / 2Kbit / 1Kbit and 256bit 8-bit or 16-bit wide
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M93C06 Hoja de datos, Descripción, Manual

M93C86, M93C76, M93C66
M93C56, M93C46
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)
MICROWIRE® Serial Access EEPROM
FEATURES SUMMARY
s Industry Standard MICROWIRE Bus
s Single Supply Voltage:
4.5 to 5.5V for M93Cx6
2.5 to 5.5V for M93Cx6-W
1.8 to 5.5V for M93Cx6-R
s Dual Organization: by Word (x16) or Byte (x8)
s Programming Instructions that work on: Byte,
Word or Entire Memory
s Self-timed Programming Cycle with Auto-
Erase
s Ready/Busy Signal During Programming
s Speed:
1MHz Clock Rate, 10ms Write Time
(Current product, identified by process
identification letter F or M)
2MHz Clock Rate, 5ms Write Time (New
Product, identified by process
identification letter W or G or S)
s Sequential Read Operation
s Enhanced ESD/Latch-Up Behaviour
s More than 1 Million Erase/Write Cycles
s More than 40 Year Data Retention
Table 1. Product List
Reference
Part
Number
M93C86
M93C86 M93C86-W
M93C86-R
M93C76
M93C76 M93C76-W
M93C76-R
M93C66
M93C66 M93C66-W
M93C66-R
Reference
Part
Number
M93C56
M93C56 M93C56-W
M93C56-R
M93C46
M93C46 M93C46-W
M93C46-R
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
August 2004
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M93C06 pdf
M93C86, M93C76, M93C66, M93C56, M93C46
An internal Power-on Data Protection mechanism
in the M93Cx6 inhibits the device when the supply
is too low.
Figure 3. DIP, SO, TSSOP and MLP
Connections (Top View)
M93Cx6
S1
C2
8 VCC
7 DU
D3
6 ORG
Q4
5 VSS
AI01929B
Note: 1. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
2. DU = Dont Use.
The DU (Dont Use) pin does not contribute to the
normal operation of the device. It is reserved for
use by STMicroelectronics during test sequences.
The pin may be left unconnected or may be con-
nected to VCC or VSS. Direct connection of DU to
VSS is recommended for the lowest stand-by pow-
er consumption.
MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to VCC)
the x16 organization is selected; when Organiza-
tion Select (ORG) is connected to Ground (VSS)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to VSS or VCC for minimum
power consumption. Any voltage between VSS
and VCC applied to Organization Select (ORG)
may increase the stand-by current.
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode.
At Power-up and Power-down, the device
must not be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltage reaches the operating value VCC
specified in Table 9. to Table 11..
When VCC reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6-
W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
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M93C06 arduino
M93C86, M93C76, M93C66, M93C56, M93C46
READY/BUSY STATUS
While the Write or Erase cycle is underway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Se-
lect Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
When the Write cycle is completed, and Chip Se-
lect Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to re-
ceive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is
brought Low or until a new start bit is decoded.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the master (the microcontrol-
ler). This can lead to a misalignment of the instruc-
tion of one or more bits (as shown in Figure 7.) and
may lead to the writing of erroneous data at an er-
roneous address.
To combat this problem, the M93Cx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Cx6
family, are summarized in Table 5. to Table 7.. For
example, a Write Data to Memory (WRITE) in-
struction on the M93C56 (or M93C66) expects 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 7. Write Sequence with One Clock Glitch
S
C
D
START
"0" "1"
WRITE
An
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395
11/31

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