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PDF 7AHCT573PWDH Data sheet ( Hoja de datos )
| Número de pieza | 7AHCT573PWDH | |
| Descripción | Octal D-type transparent latch; 3-state | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
74AHC573; 74AHCT573
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
1999 Sep 27
1 page  
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74AHC573; 74AHCT573
D0 D1 D2 D3 D4 D5 D6 D7
DQ
LATCH
1
LE
DQ
LATCH
2
LE
DQ
LATCH
3
LE
DQ
LATCH
4
LE
DQ
LATCH
5
LE
DQ
LATCH
6
LE
DQ
LATCH
7
LE
DQ
LATCH
8
LE
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MNA392
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VO
Tamb
tr,tf (∆t/∆f)
DC supply voltage
input voltage
output voltage
operating ambient
temperature range
input rise and fall rates
CONDITIONS
74AHC
74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
2.0 5.0 5.5 4.5 5.0 5.5 V
0 − 5.5 0 − 5.5 V
0 − VCC 0 − VCC V
see DC and AC
−40 +25 +85 −40 +25 +85 °C
characteristics per device −40 +25 +125 −40 +25 +125 °C
VCC = 3.3 V ±0.3 V
− − 100 − − − ns/V
VCC = 5 V ±0.5 V
− − 20 − − 20
1999 Sep 27
5
5 Page 
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74AHC573; 74AHCT573
74AHCT573
GND = 0 V; tr = tf ≤ 3.0 ns.
SYMBOL PARAMETER
TEST CONDITIONS
WAVEFORMS
CL
Tamb (°C)
25 −40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH propagation delay see Figs 6 and 9
Dn to Qn
15 pF −
3.5 5.5 1
6.5 1
7.0 ns
propagation delay see Figs 7 and 9
− 3.9 6.0 1 7.0 1
7.5 ns
LE to Qn
tPZH/tPZL propagation delay see Figs 8 and 9
OE to Qn
− 4.1 6.5 1 7.5 1
8.5 ns
tPHZ/tPLZ propagation delay
OE to Qn
− 4.5 6.5 1 7.5 1
8.5 ns
tPHL/tPLH propagation delay see Figs 6 and 9
Dn to Qn
50 pF −
4.9 7.5 1
8.5 1
9.5 ns
propagation delay see Figs 7 and 9
− 5.5 8.5 1 9.5 1
11.0 ns
LE to Qn
tPZH/tPZL propagation delay see Figs 8 and 9
OE to Qn
− 5.9 8.5 1 10.0 1
11.0 ns
tPHZ/tPLZ propagation delay
OE to Qn
− 6.4 9.0 1 10.0 1
11.5 ns
tW enable pulse width see Figs 7 and 9
HIGH
5.0 − − 5.0 − 5.0 − ns
tsu set-up time see Fig.9
Dn to LE
th hold time
Dn to LE
3.5 − − 3.5 − 3.5 − ns
1.5 − − 1.5 − 1.5 − ns
Note
1. Typical values at VCC = 5.0 V.
1999 Sep 27
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 7AHCT573PWDH.PDF ] | |
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