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PDF M87C51FC Data sheet ( Hoja de datos )
| Número de pieza | M87C51FC | |
| Descripción | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 32 KBYTES USER PROGRAMMABLE EPROM | |
| Fabricantes | Intel | |
| Logotipo |  |
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M87C51FC
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 32 KBYTES USER PROGRAMMABLE EPROM
Military
M87C51FC 3 5 MHz to 12 MHz VCC e 5Vg20%
M87C51FC-1 3 5 MHz to 16 MHz VCC e 5Vg20%
Y High Performance CHMOS EPROM
Y Three 16-Bit Timer Counters
Y Programmable Clock Out
Y Programmable Counter Array with
High Speed Output
Compare Capture
Pulse Width Modulator
Watchdog Timer Capabilities
Y Up Down Timer Counter
Y Three Level Program Lock System
Y 32K On-Chip EPROM
Y 256 Bytes of On-Chip Data RAM
Y Improved Quick Pulse Programming
Algorithm
Y Boolean Processor
Y Available in 40-pin Cerdip and 44-pin
LCC Packages
Y 32 Programmable I O Lines
Y 7 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS -51 Fully Compatible Instruction
Set
Y Power Saving Idle and Power Down
Modes
Y ONCE (On-Circuit Emulation) Mode
Y Available in Two Product Grades
MIL-STD-883 b55 C to a125 C (TC)
Military Temperature Only (MTO)
b55 C to a125 C (TC)
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 32 Kbytes of the program memory can reside in the on-chip EPROM In addition
the device can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel M87C51FC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS III-E technology Being a member of the MCS-51 family the M87C51FC uses the same powerful
instruction set has the same architecture and is pin-for-pin compatible with the existing MCS-51 family of
products The M87C51FC is an enhanced version of the 87C51 Its added features make it an even more
powerful microcontroller for applications that require Pulse Width Modulation High Speed I O and up down
counting capabilities such as motor control It also has a more versatile serial channel that facilitates multi-
processor communications
January 1994
Order Number 271114-004
1 page  
M87C51FC
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
271114 – 5
Figure 4 External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timer counter can
optionally be left running or paused during Idle
Mode
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the M87C51FC either a hardware reset or an
external interrupt can cause an exit from Power
Down Reset redefines all the SFRs but does not
change the on-chip RAM An external interrupt al-
lows both the SFRs and on-chip RAM to retain their
values
To properly terminate Power down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
DESIGN CONSIDERATION
The window on the M87C51FC must be covered
by an opaque label Otherwise the DC and AC
characteristics may not be met and the device
may functionally be impaired
When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
M87C51FC without the M87C51FC having to be re-
moved from the circuit The ONCE Mode is invoked
by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
go into a float state and the other port pins and ALE
and PSEN are weakly pulled high The oscillator cir-
cuit remains active While the M87C51FC is in this
mode an emulator or test CPU can be used to drive
the circuit Normal operation is restored when a nor-
mal reset is applied
Mode
Idle
Idle
Power Down
Power Down
Table 1 Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
Internal
1
1
Data
Data
Data
External
1
1
Float
Data
Address
Internal
0
0
Data
Data
Data
External
0
0
Float
Data
Data
PORT3
Data
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to Application Note AP-255 ‘‘Military CHMOS Designing
with the M80C51BH ’’
5
5 Page 
M87C51FC
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions TC e b55 C to a125 C VCC e 5V g10% VSS e 0V Load Capacitance e 80 pF
Symbol
Parameter
12 MHz
Oscillator
Min Max
16 MHz
Oscillator
Min Max
Variable
Oscillator
Min Max
Units
TXLXL Serial Port Clock
Cycle Time
1
0 75
12TCLCL
ms
TQVXH Output Data Setup to 700 492 10TCLCLb133
Clock Rising Edge
ns
TXHQX Output Data Hold After 50 8 2TCLCLb117
Clock Rising Edge
ns
TXHDX Input Data Hold After
Clock Rising Edge
0
0
0
ns
TXHDV Clock Rising Edge to
Input Data Valid
700 492
10TCLCLb133 ns
SHIFT REGISTER MODE TIMING WAVEFORMS
271114 – 14
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min Max Units
1 TCLCL
Oscillator Frequency
M87C51FC
M87C51FC-16
35
35
12
16
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20 ns
TCHCL
Fall Time
20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
271114 – 15
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M87C51FC.PDF ] | |
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