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PDF M80C86 Data sheet ( Hoja de datos )
| Número de pieza | M80C86 | |
| Descripción | 16-BIT CHMOS MICROPROCESSOR | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80C86 M80C86-2
16-BIT CHMOS MICROPROCESSOR
MILITARY
Y Pin-for-Pin and Functionally Compatible
to Industry Standard HMOS M8086
Y Fully Static Design with Frequency
Range from D C to
5 MHz for M80C86
8 MHz for M80C86-2
Y Low Power Operation
Operating ICC e 10 mA MHz
Standby ICCS e 500 mA max
Y Bus-Hold Circuitry Eliminates Pull-Up
Resistors
Y Direct Addressing Capability of
1 MByte of Memory
Y Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y 24 Operand Addressing Modes
Y Byte Word and Block Operations
Y 8 and 16-Bit Signed and Unsigned
Arithmetic
Binary or Decimal
Multiply and Divide
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C86 is a high performance CHMOS version of the industry standard HMOS M8086 16-bit CPU It
is available in 5 and 8 MHz clock rates The M80C86 offers two modes of operation MINimum for small
systems and MAXimum for larger applications such as multiprocessing It is available in 40-pin DIP package
271058 –1
Figure 1 M80C86 CPU Block Diagram
271058 – 2
Figure 2 M80C86 40-Lead DIP Configuration
November 1989
Order Number 271058-005
1 page  
M80C86 M80C86-2
Symbol
LOCK
QS1 QS0
Pin No
29
24 25
Table 1 Pin Description (Continued)
Type
Name and Function
If the local bus is idle when the request is made the two possible
events will follow
1 Local bus will be released during the next clock
2 A memory cycle will start within 3 clocks Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied
O LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK
signal is activated by the ‘‘LOCK’’ prefix instruction and remains
active until the completion of the next instruction This signal is active
LOW and floats to 3-state OFF(1) in ‘‘hold acknowledge ’’
O QUEUE STATUS The queue status is valid during the CLK cycle
after which the queue operation is performed
QS1 and QS0 provide status to allow external tracking of the internal
M80C86 instruction queue
QS1
0 (LOW)
0
1 (HIGH)
1
QS0 Characteristics
0 No Operation
1 First Byte of Op Code from Queue
0 Empty the Queue
1 Subsequent Byte from Queue
The following pin function descriptions are for the M80C86 in minimum mode (i e MN MX eVCC ) Only the
pin functions which are unique to minimum mode are described all other pin functions are described above
M IO
WR
INTA
ALE
DT R
28 O STATUS LINE logically equivalent to S2 in the maximum mode It
is used to distinguish a memory access from an I O access M IO
becomes valid in the T4 preceding a bus cycle and remains valid
until the final T4 of the cycle (MeHIGH IOeLOW) M IO floats to
3-state OFF(1) in local bus ‘‘hold acknowledge ’’
29 O WRITE indicates that the processor is performing a write memory
or write I O cycle depending on the state of the M IO signal WR is
active for T2 T3 and TW of any write cycle It is active LOW and
floats to 3-state OFF(1) in local bus ‘‘hold acknowledge ’’
24 O INTA is used as a read strobe for interrupt acknowledge cycles It is
active LOW during T2 T3 and TW of each interrupt acknowledge
cycle
25 O ADDRESS LATCH ENABLE provided by the processor to latch
the address into an address latch It is a HIGH pulse active during
T1 of any bus cycle Note that ALE is never floated
27 O DATA TRANSMIT RECEIVE needed in minimum system that
desires to use a data bus transceiver It is used to control the
direction of data flow through the transceiver Logically DT R is
equivalent to S1 in the maximum mode and its timing is the same
as for M IO (TeHIGH ReLOW ) This signal floats to 3-state
OFF(1) in local bus ‘‘hold acknowledge ’’
5
5 Page 
M80C86 M80C86-2
A C CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Timing Responses
Symbol
Parameter
TCLAV
TCLAX
TCLAZ
TLHLL
TCLLH
TCHLL
TLLAX
TCLDV
TCHDX
TWHDX
TCVCTV
TCHCTV
TCVCTX
TAZRL
TCLRL
TCLRH
TRHAV
TCLHAV
TRLRH
TWLWH
TAVAL
TOLOH
TOHOL
Address Valid Delay
Address Hold Time
Address Float
Delay
ALE Width
ALE Active Delay
ALE Inactive Delay
Address Hold Time
to ALE Inactive
Data Valid Delay
Data Hold Time
Data Hold Time
After WR
Control Active
Delay 1
Control Active
Delay 2
Control Inactive
Delay
Address Float to
READ Active
RD Active Delay
RD Inactive Delay
RD Inactive to Next
Address Active
HLDA Valid Delay
RD Width
WR Width
Address Valid to
ALE Low
Output Rise Time
Output Fall Time
M80C86
Min Max
10 110
10
TCLAX
80
TCLCHb20
TCHCLb10
80
85
10
10
TCLCHb30
110
10 110
10 110
10 110
0
10
10
TCLCLb45
165
150
10
2TCLCLb75
2TCLCLb60
TCLCHb60
160
15
15
M80C86-2
Min Max
10 60
10
TCLAX
50
TCLCHb10
TCHCLb10
50
55
10
10
TCLCHb30
60
10 70
10 60
10 70
0
10
10
TCLCLb40
100
80
10
2TCLCLb50
2TCLCLb40
TCLCHb40
100
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
From 0 8V to 2 0V
From 2 0V to 0 8V
NOTES
1 Signal at M82C84A shown for reference only See M82C84A data sheet for the most recent specifications
2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK
3 Applies only to T2 state (5 ns into T3)
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet M80C86.PDF ] | |
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