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PDF M80C51FB Data sheet ( Hoja de datos )
| Número de pieza | M80C51FB | |
| Descripción | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80C51FB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Military
M80C51FB 3 5 MHz to 12 MHz VCC e 5V
g20%
M80C51FB-16 3 5 MHz to 16 MHz VCC e
5V g20%
Y Three 16-Bit Timer Counters
Y Programmable Clock Out
Y Programmable Counter Array with
High Speed Output
Compare Capture
Pulse Width Modulator
Watchdog Timer capabilities
Y Up Down Timer Counter
Y 256 Bytes of On-Chip Data RAM
Y Boolean Processor
Y ONCE (On-Circuit Emulation) Mode
Y Available in 40-pin CERDIP and
44-pin Leadless Chip Carrier Packages
Y Gull Wing and J-Lead Packages also
Available
Y 32 Programmable I O Lines
Y 7 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS 51 Microcontroller Fully
Compatible Instruction Set
Y Power Saving Idle and Power Down
Modes
Y Military Temperature Range
b55 C to a125 C (TC)
MEMORY ORGANIZATION
PROGRAM MEMORY The M80C51FB can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64K bytes of
external data memory
The Intel M80C51FB is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS III-E technology Being a member of the family of MCS 51 microcontrollers the M80C51FB uses the
same powerful instruction set has the same architecture and is pin for pin compatible with the existing
MCS 51 microcontroller family of products The M80C51FB is an enhanced version of the M80C51 Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation
High Speed I O and up down counting capabilities such as motor control or fin actuation It also has a more
versatile serial channel that facilitates multi-processor communications
October 1994
Order Number 271172-002
1 page  
M80C51FB
271172 –5
Figure 4 External Clock Drive Configuration
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that
puts the device into Power Down
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timer counter can
optionally be left running or paused during Idle
Mode
DESIGN CONSIDERATION
When the Idle Mode is terminated by a hardware
reset the device normally resumes program execu-
tion from where it left off up to two machine cycles
before the internal reset algorithm takes control On-
chip hardware inhibits access to internal RAM in this
event but access to the port pins is not inhibited To
eliminate the possibility of an unexpected write when
Idle is terminated by reset the instruction following
the one that invokes Idle should not be one that
writes to a port pin or to external memory
POWER DOWN MODE
To save even more power a Power Down Mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down Mode is terminated
On the M80C51FB either a hardware reset or an
external interrupt can cause an exit from Power
Down Reset redefines all the SFRs but does not
change the on-chip RAM An external interrupt al-
lows both the SFRs and on-chip RAM to retain their
values
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
M80C51FB without the M80C51FB having to be re-
moved from the circuit The ONCE Mode is invoked
by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
go into a float state and the other port pins and ALE
and PSEN are weakly pulled high The oscillator cir-
cuit remains active While the M80C51FB is in this
mode an emulator or test CPU can be used to drive
the circuit Normal operation is restored when a nor-
mal reset is applied
Mode
Idle
Power Down
Table 1 Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
External
1
1
Float
Data
Address
External
0
0
Float
Data
Data
PORT3
Data
Data
NOTE
For more detailed information on the reduced power modes refer to current 8-Bit Embedded Controller Handbook and
Application Note AP-255 ‘‘Designing with the M80C51BH ’’
5
5 Page 
M80C51FB
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions (Over Specified Operating Conditions)
Symbol
Parameter
12 MHz 16 MHz
Oscillator Oscillator
Variable
Oscillator
Units
Min Max Min Max
Min
Max
TXLXL Serial Port Clock Cycle Time 1
0 75
12TCLCL
ms
TQVXH Output Data Setup to Clock 700 492 10TCLCLb133
Rising Edge
ns
TXHQX Output Data Hold after
50
8
2TCLCLb117
Clock Rising Edge
ns
TXHDX Input Data Hold After Clock 0
Rising Edge
0
0
ns
TXHDV Clock Rising Edge to Input
Data Valid
700 492
10TCLCLb133 ns
SHIFT REGISTER MODE TIMING WAVEFORMS
271172 – 13
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M80C51FB.PDF ] | |
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