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PDF M80C287 Data sheet ( Hoja de datos )
| Número de pieza | M80C287 | |
| Descripción | 80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80C287
80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION
Military
Y High Performance 80-Bit Internal
Architecture
Y Implements ANSI IEEE Standard 754-
1985 for Binary Floating-Point
Arithmetic
Y Implements Extended M387 Numerics
Coprocessor Instruction Set
Y Two to Three Times M8087 M80287
Performance at Equivalent Clock Speed
Y Low Power Consumption
Y Upward Object-Code Compatible from
M8087 and M80287
Y Interfaces with M80286 and M80C286
CPUs
Y Expands CPU’s Data Types to Include
32- 64- 80-Bit Floating Point 32- 64-
Bit Integers and 18-Digit BCD Operands
Y Directly Extends CPU’s Instruction Set
to Trigonometric Logarithmic
Exponential and Arithmetic
Instructions for All Data Types
Y Full-Range Transcendental Operations
for SINE COSINE TANGENT
ARCTANGENT and LOGARITHM
Y Built-In Exception Handling
Y Operates in Both Real and Protected
Mode Systems
Y Eight 80-Bit Numeric Registers Usable
as Individually Addressable General
Registers or as a Register Stack
Y Available in 40-pin CERDIP
(See Packaging Outlines and Dimensions order 231369)
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C287 is a high-performance numerics processor extension that extends the architecture of the
M80C286 CPU with floating point extended integer and BCD data types A computing system that includes
the M80C287 fully conforms to the IEEE Floating Point Standard Using a numerics oriented architecture the
M80C287 adds over seventy mnemonics to the instruction set of the M80C286 CPU making a complete
solution for high-performance numerics processing The M80C287 is implemented with 1 5 micron high-speed
CHMOS III technology and packaged in a 40-pin CERDIP The M80C287 is upward object-code compatible
from the M80287 and M8087 numerics coprocessors With proper socket design either an M80287 or an
M80C287 can use the same socket
November 1991
Figure 1 M80C287 Block Diagram
271092 – 1
Order Number 271092-005
1 page  
M80C287
Figure 4 shows the six exception flags in bits 5– 0 of
the status word Bits 5– 0 are set to indicate that the
M80C287 has detected an exception while execut-
ing an instruction A later section entitled ‘‘Exception
Handling’’ explains how they are set and used
Note that when a new value is loaded into the status
word by the FLDENV or FRSTOR instruction the
value of ES (bit 7) and its reflection in the B-bit (bit
15) are not derived from the values loaded from
memory but rather are dependent upon the values of
the exception flags (bits 5 – 0) in the status word and
their corresponding masks in the control word If ES
is set in such a case the ERROR output of the
M80C287 is activated immediately
ES is set if any unmasked exception bit is set cleared otherwise
See Table 2 2 for interpretation of condition code
TOP Values
000 e Register 0 is Top of Stack
001 e Register 1 is Top of Stack
111 e Register 7 is Top of Stack
For definitions of exceptions refer to the section entitled ‘‘Exception Handling ’’
Figure 4 Status Word
271092 – 3
5
5 Page 
M80C287
Many changes have been designed into the
M80C287 to directly support the IEEE standard in
hardware These changes result in increased per-
formance by eliminating the need for software that
supports the standard
GENERAL DIFFERENCES
The M80C287 supports only affine closure for infini-
ty arithmetic not projective closure
Operands for FSCALE and FPATAN are no longer
restricted in range (except for g %) F2XM1 and
FPTAN accept a wider range of operands
Rounding control is in effect for FLD constant
Software cannot change entries of the tag word to
values (other than empty) that differ from actual reg-
ister contents
After reset FINIT and incomplete FPREM the
M80C287 resets to zero the condition code bits C3 –
C0 of the status word
In conformance with the IEEE standard the
M80C287 does not support the special data formats
pseudozero pseudo-NaN pseudoinfinity and un-
normal
The denormal exception has a different purpose on
the M80C287 A system that uses the denormal-ex-
ception handler solely to normalize the denormal op-
erands would better mask the denormal exception
on the M80C287 The M80C287 automatically nor-
malizes denormal operands when the denormal ex-
ception is masked
EXCEPTIONS
A number of differences exist due to changes in the
IEEE standard and to functional improvements to
the architecture of the M80C287
1 When the overflow or underflow exception is
masked the M80C287 differs from the M80287
in rounding when overflow or underflow occurs
The M80C287 produces results that are consist-
ent with the rounding mode
2 When the underflow exception is masked the
M80C287 sets its underflow flag only if there is
also a loss of accuracy during denormalization
3 Fewer invalid-operation exceptions due to de-
normal operands because the instructions
FSQRT FDIV FPREM and conversions to BCD
or to integer normalize denormal operands be-
fore proceeding
4 The FSQRT FBSTP and FPREM instructions
may cause underflow because they support de-
normal operands
5 The denormal exception can occur during the
transcendental instructions and the FXTRACT
instruction
6 The denormal exception no longer takes prece-
dence over all other exceptions
7 When the denormal exception is masked the
M80C287 automatically normalizes denormal
operands The M8087 M80287 performs unnor-
mal arithmetic which might produce an unnor-
mal result
8 When the operand is zero the FXTRACT in-
struction reports a zero-divide exception and
leaves b % in ST(1)
9 The status word has a new bit (SF) that signals
when invalid-operation exceptions are due to
stack underflow or overflow
10 FLD extended precision no longer reports denor-
mal exceptions because the instruction is not
numeric
11 FLD single double precision when the operand
is denormal converts the number to extended
precision and signals the denormalized operand
exception When loading a signalling NaN FLD
single double precision signals an invalid-oper-
and exception
12 The M80C287 only generates quiet NaNs (as on
the M80287) however the M80C287 distin-
guishes between quiet NaNs and signaling
NaNs Signaling NaNs trigger exceptions when
they are used as operands quiet NaNs do not
(except for FCOM FIST and FBSTP which also
raise IE for quiet NaNs)
13 When stack overflow occurs during FPTAN and
overflow is masked both ST(0) and ST(1) con-
tain quiet NaNs The M8087 M80287 leaves the
original operand in ST(1) intact
14 When the scaling factor is g % the FSCALE
(ST(0) ST(1)) instruction behaves as follows
(ST(0) and ST(1) contain the scaled and scaling
operands respectively)
FSCALE(0 %) generates the invalid operation
exception
FSCALE(finite b%) generates zero with the
same sign as the scaled operand
FSCALE(finite a %) generates -in with the
same sign as the scaled operand
The M8087 M80287 returns zero in the first
case and raises the invalid-operation exception
in the other cases
11
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| PDF Descargar | [ Datasheet M80C287.PDF ] | |
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