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PDF M80C186EB-16 Data sheet ( Hoja de datos )
| Número de pieza | M80C186EB-16 | |
| Descripción | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80C186EB-16 -13 -8
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Full Static Operation
True CMOS Inputs and Outputs
b55 C to a125 C Operating Temperature Range
Y Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Speed Versions Available
16 MHz (M80C186EB-16)
13 MHz (M80C186EB-13)
8 MHz (M80C186EB-8)
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y Complete System Development
Support
ASM86 Assembler PL M 86 Pascal
86 Fortran 86 C-86 and System
Utilities
In-Circuit Emulator (ICETM-186EB)
Y Supports M80C187 Numeric
Coprocessor Interface
Y Available In
88-Lead Pin Grid Array
(MG80C186EB)
The M80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are
new to the M80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two
independent Serial Channels I O ports and the capability of Idle or Powerdown low power modes
April 1990
271214 – 1
Order Number 271214-002
1 page  
M80C186EB
INSTRUCTION SET
The instruction set is divided into seven categories
data transfer arithmetic shift rotate logical string
manipulation control transfer high-level instruc-
tions and processor control These categories are
summarized in Figure 4
An M80C186EB instruction can reference anywhere
from zero to several operands An operand can
reside in a register in the instruction itself or in
memory
MEMORY ORGANIZATION
Memory is organized in sets of segments Each seg-
ment is a linear contiguous sequence of up to 64K
(216) 8-bit bytes Memory is addressed using a two-
component address (a pointer) that consists of a
16-bit base segment and a 16-bit offset The 16-bit
base segment values are contained in one of four
internal segment registers (code data stack extra)
The physical address is calculated by shifting the
base value left by four bits and adding the 16-bit
offset value to yield a 20-bit physical address (see
Figure 3) The resulting 20-bit address allows for a
1 Mbyte address range
271214 –3
Figure 3 Two Component Address
All instructions that address operands in memory
must specify the base segment and the 16-bit offset
value For speed and compact instruction encoding
the segment register used for a physical address
generation is implied by the addressing mode used
(see Table 1) Special segment override instruction
prefixes allow the implicit segment register selection
rules to be overridden for special cases The code
stack data and extra segments may coincide for
simple programs
Table 1 Segment Register Selection Rules
Memory Segment
Reference Register
Needed Used
Implicit Segment
Selection Rule
Instructions Code (CS) Instruction prefetch and
immediate data
Stack
Stack (SS) All stack pushes and pops
any memory references
which use the BP register
as a base
External Extra (ES) All String instruction
references which use the
DI register as an index
Local Data Data (DS) All other data references
ADDRESSING MODES
The M80C186EB provides eight categories of ad-
dressing modes to specify operands Two address-
ing modes are provided for instructions that operate
on register or immediate operands
Register Operand Mode The operand is located
in one of the 8- or 16-bit general registers
Immediate Operand Mode The operand is in-
cluded in the instruction
Six modes are provided to specify the location of an
operand in a memory segment A memory operand
address consists of two 16-bit components a seg-
ment base and an offset The segment base is sup-
plied by a 16-bit segment register either implicitly
chosen by the addressing mode or explicitly chosen
by a segment override prefix The offset also called
the effective address is calculated by summing any
combination of the following three address ele-
ments
the displacement (an 8- or 16-bit immediate value
contained in the instruction)
the base (contents of either the BX or BP base
registers) and
the index (contents of either the SI or DI index
registers)
5
5 Page 
M80C186EB
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
00H Reserved
40H Timer2 Count
80H GCS0 Start
C0H
02H End Of Interrupt
42H Timer2 Compare 82H GCS0 Stop
C2H
04H Poll
44H Reserved
84H GCS1 Start
C4H
06H Poll Status
46H Timer2 Control
86H GCS1 Stop
C6H
08H Interrupt Mask
48H Reserved
88H GCS2 Start
C8H
0AH Priority Mask
4AH
Reserved
8AH
GCS2 Stop
CAH
0CH
In-Service
4CH
Reserved
8CH
GCS3 Start
CCH
0EH Interrupt Request
4EH
Reserved
8EH
GCS3 Stop
CEH
10H Interrupt Status 50H Reserved
90H GCS4 Start
D0H
12H Timer Control
52H Port0 Pin
92H GCS4 Stop
D2H
14H Serial Control
54H Port0 Control
94H GCS5 Start
D4H
16H INT4 Control
56H Port0 Latch
96H GCS5 Stop
D6H
18H INT0 Control
58H Port1 Direction
98H GCS6 Start
D8H
1AH INT1 Control
5AH
Port1 Pin
9AH
GCS6 Stop
DAH
1CH INT2 Control
5CH Port1 Control
9CH
GCS7 Start
DCH
1EH INT3 Control
5EH Port1 Latch
9EH
GCS7 Stop
DEH
20H Reserved
60H Serial0 Baud
A0H
LCS Start
E0H
22H Reserved
62H Serial0 Count
A2H
LCS Stop
E2H
24H Reserved
64H Serial0 Control A4H UCS Start
E4H
26H Reserved
66H Serial0 Status
A6H
UCS Stop
E6H
28H Reserved
68H Serial0 RBUF
A8H
Relocation
E8H
2AH
Reserved
6AH Serial0 TBUF
AAH
Reserved
EAH
2CH
Reserved
6CH
Reserved
ACH
Reserved
ECH
2EH Reserved
6EH Reserved
AEH
Reserved
EEH
30H Timer0 Count
70H Serial1 Baud
B0H Refresh Base
F0H
32H Timer0 Compare A 72H Serial1 Count
B2H Refresh Time
F2H
34H Timer0 Compare B 74H Serial1 Control
B4H Refresh Control
F4H
36H Timer0 Control
76H Serial1 Status
B6H Refresh Address
F6H
38H Timer1 Count
78H Serial1 RBUF
B8H Power Control
F8H
3AH Timer1 Compare A 7AH Serial1 TBUF
BAH
Reserved
FAH
3CH Timer1 Compare B 7CH
Reserved
BCH
Step ID
FCH
3EH Timer1 Control
7EH Reserved
BEH
Reserved
FEH
Figure 6 M80C186EB Peripheral Control Block Registers
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
11 Page | ||
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