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PDF M74HCT74 Data sheet ( Hoja de datos )

Número de pieza M74HCT74
Descripción DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M54HCT74
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 53 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS74
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C2MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption. A signal on
the D INPUT is transferred to the Q OUTPUT during
the positive going transition of the clock pulse.
CLEAR and PRESET are independent of the clock
and accomplished by a low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age. This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are de-
signed to directly interface HSC2MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
ORDER CODES :
M54HCT74F1R
M74HCT74M1R
M74HCT74B1R
M 74H CT 7 4C 1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
February 1993
NC =
No Internal
Connection
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1 page




M74HCT74 pdf
M54/M74HCT74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 4.5
tTHL Time
tPLH Propagation
tPHL Delay Time
(CLOCK - Q)
4.5
8 15 19 22 ns
21 33 41 50
ns
tPLH Propagation
4.5
tPHL Delay Time
(CL, PR - Q, Q)
18 30 38 45
ns
fMAX Maximum Clock 4.5
Frequency
27 48 22 18 MHz
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
4.5
6 15 19 23
ns
tW(L) Minimum Pulse
Width
(CL, PR)
4.5
8 15 19 23
ns
ts Minimum Set-up 4.5
Time
7 15 19 23 ns
th Minimum Hold 4.5
Time
0 0 0 ns
tREM Minimum
Removal Time
(CL, PR)
4.5
155658
ns
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
32
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/2 (per FLIP/FLOP)
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M74HCT74 arduino
M54/M74HCT74
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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