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PDF M74ACT574B Data sheet ( Hoja de datos )

Número de pieza M74ACT574B
Descripción OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
Fabricantes ST Microelectronics 
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® 74ACT574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC = 3.3V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
PACKAGE
DIP
SOP
TSSOP
SOP
TSSOP
ORDER CODES
T UB E
T&R
M74ACT574B
M74ACT574M M74ACT574MTR
M74ACT574TTR
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
The device is designed to interface directly High
Speed CMOS system with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2000
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M74ACT574B pdf
74ACT574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf =3 ns)
Symb ol
Parameter
tPLH Propagation Delay Time
tPHL CK to Q
tPZL Output Enable Time
tPZH
tPLH Output Disable Time
tPHL
tw CK Pulse Width, HIGH
or LOW
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
fMAX Maximim Clock
Frequency
(*) Voltage range is 5V ± 0.5V
T est Con ditio n
VCC
(V)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
5.0 10.0
11.0
Unit
ns
5.5 9.0
10.0 ns
5.0 8.5
9.0 ns
1.5 3.0
4.0 ns
1.0 2.5
3.0 ns
-1.0 2.5
3.0 ns
100 250 85 MHz
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
COUT Output Capacitance
5.0
8 pF
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0
26 pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/n (per circuit)
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M74ACT574B arduino
74ACT574
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2000 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
.
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