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PDF M68Z512-70NC1T Data sheet ( Hoja de datos )
| Número de pieza | M68Z512-70NC1T | |
| Descripción | 4 Mbit 512Kb x8 Low Power SRAM with Output Enable | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M68Z512
4 Mbit (512Kb x8) Low Power SRAM with Output Enable
s ULTRA LOW DATA RETENTION CURRENT
– 100nA (typical)
– 10µA (max)
s OPERATION VOLTAGE: 5V ±10%
s 512 Kbit x8 SRAM with OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIMES: 70ns
s LOW VCC DATA RETENTION: 2V
s TRI-STATE COMMON I/O
s CMOS for OPTIMUM SPEED/POWER
s AUTOMATIC POWER-DOWN WHEN
DESELECTED
s INTENDED FOR USE WITH ST
ZEROPOWER® AND TIMEKEEPER®
CONTROLLERS
DESCRIPTION
The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68Z512 is available in a 32 lead TSOP II
(10 x 20mm) package.
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Output
E Chip Enable
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
32
1
TSOP II 32 (NC)
10 x 20mm
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W M68Z512
E
G
VSS
AI03030
March 2000
1/12
1 page  
M68Z512
Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 5V ±10%)
M68Z512
Symbol
Parameter
-70 Unit
Min Max
tAVAV Read Cycle Time
70 ns
tAVQV (1) Address Valid to Output Valid
70 ns
tELQV (1) Chip Enable Low to Output Valid
70 ns
tGLQV (1) Output Enable Low to Output Valid
35 ns
tELQX (3) Chip Enable Low to Output Transition
10 ns
tGLQX (3) Output Enable Low to Output Transition
5 ns
tEHQZ (2,3) Chip Enable High to Output Hi-Z
25 ns
tGHQZ (2,3) Output Enable High to Output Hi-Z
25 ns
tAXQX (1) Address Transition to Output Transition
10 ns
tPU Chip Enable Low to Power Up
0 ns
tPD Chip Enable High to Power Down
70 ns
Note: 1. CL = 100pF.
2. CL = 5pF.
3. At any given temperature and voltage condition, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for any given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
A0-A18
DQ0-DQ7
tAVQV
tAVAV
VALID
DATA VALID
tAXQX
AI03034
Note: E = Low, G = Low, W = High.
5/12
5 Page 
M68Z512
Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm inch
Symbol
Typ Min Max Typ Min Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
b
0.30
0.52
0.012
0.020
C
0.12
0.21
0.005
0.008
CP
0.10
0.004
D
20.82
21.08
0.820
0.830
e 1.27 –
– 0.050 –
–
E
11.56
11.96
0.455
0.471
E1
10.03
10.29
0.395
0.405
L
0.40
0.60
0.016
0.024
α 0° 5° 0° 5°
N 32
32
Figure 11. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
16
17
b
A
CP
Drawing is not to scale.
1
E1 E
32
e
A2
A1 α
C
L
TSOP-d
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M68Z512-70NC1T.PDF ] | |
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