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PDF M68HC11KA Data sheet ( Hoja de datos )

Número de pieza M68HC11KA
Descripción 8-Bit Microcontroller
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! M68HC11KA Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document
by MC68HC11KA4TS/D
M68HC11 KA Series
Technical Summary
8-Bit Microcontroller
www.DataSheet4U.com
1 Introduction
The MC68HC11KA4 family of microcontrollers are enhanced derivatives of the MC68HC11F1 and, as
shown in the block diagram, include many additional features. The family includes the MC68HC11KA0,
MC68HC11KA1, MC68HC11KA3, MC68HC11KA4, MC68HC711KA4, MC68HC11KA2, and the
MC68HC711KA2. These MCUs, with a non-multiplexed expanded bus, are characterized by high
speed and low power consumption. The fully static design allows operation at frequencies from 4 MHz
to dc.
This technical summary contains information concerning standard, custom-ROM, and extended-volt-
age devices. Standard devices are those with disabled ROM (MC68HC11KA1), disabled EEPROM
(MC68HC11KA0), and EPROM replacing ROM (MC68HC711KA4). The MC68HC11KA2 and
MC68HC711KA2 contain 32 Kbytes of ROM/EPROM instead of 24 Kbytes. Custom-ROM devices have
a ROM array that is programmed at the factory to customer specifications. Extended-voltage devices
are guaranteed to operate over a much greater voltage range (3.0 Vdc to 5.5 Vdc) at lower frequencies
than the standard devices. Refer to the ordering information on the following pages.
In this summary, ROM/EPROM refers to ROM for ROM-based devices and refers to EPROM for
EPROM-based devices.
1.1 Features
• M68HC11 Central Processing Unit (CPU)
• Power Saving STOP and WAIT Modes
• 768 Bytes RAM in MC68HC11KA4, 1024 Bytes RAM in MC68HC11KA2 (Saved During Standby)
• 640 Bytes Electrically Erasable Programmable ROM (EEPROM)
• 24 Kbytes ROM/EPROM, 32 Kbytes ROM/EPROM in MC68HC11KA2
• PROG Mode Allows Use of Standard EPROM Programmer (27256 Footprint)
• Non-multiplexed Address and Data Buses
• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Four 8-Bit or Two 16-Bit Pulse-Width Modulation (PWM) Timer Channels
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter (Four Channels on 64-Pin Version)
• Seven Bidirectional Input/Output (I/O) Ports (43 Pins)
• One Fixed Input-Only Port (8 Pins, 4 Pins on 64-Pin Version)
• Available in 68-Pin Plastic Leaded Chip Carrier (Custom ROM/OTPROM), 68-Pin Windowed Ce-
ramic Leaded Chip Carrier (EPROM), or 64-Pin Quad Flat Pack (Custom ROM/OTPROM)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1996

1 page




M68HC11KA pdf
Package
68-Pin Plastic
Leaded Chip
Carrier
Table 2 Custom ROM Device Ordering Information
Temperature
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
Description
24 Kbytes Custom ROM
24 Kbytes Custom ROM
24 Kbytes Custom ROM
32 Kbytes Custom ROM
32 Kbytes Custom ROM
32 Kbytes Custom ROM
24 Kbytes Custom ROM,
No EEPROM
24 Kbytes Custom ROM,
No EEPROM
24 Kbytes Custom ROM,
No EEPROM
Frequency
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
MC Order Number
MC68HC11KA4CFN2
MC68HC11KA4CFN3
MC68HC11KA4CFN4
MC68HC11KA4VFN2
MC68HC11KA4VFN3
MC68HC11KA4VFN4
MC68HC11KA4MFN2
MC68HC11KA4MFN3
MC68HC11KA4MFN4
MC68HC11KA2CFN2
MC68HC11KA2CFN3
MC68HC11KA2CFN4
MC68HC11KA2VFN2
MC68HC11KA2VFN3
MC68HC11KA2VFN4
MC68HC11KA2MFN2
MC68HC11KA2MFN3
MC68HC11KA2MFN4
MC68HC11KA3CFN2
MC68HC11KA3CFN3
MC68HC11KA3CFN4
MC68HC11KA3VFN2
MC68HC11KA3VFN3
MC68HC11KA3VFN4
MC68HC11KA3MFN2
MC68HC11KA3MFN3
MC68HC11KA3MFN4
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
5

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M68HC11KA arduino
2 Operating Modes and On-Chip Memory
2.1 Operating Modes
In single-chip operating mode, the MC68HC11KA4 is a stand-alone microcontroller with no external ad-
dress or data bus.
In expanded non-multiplexed operating mode, the MCU can access a 64 Kbyte physical address space.
This space includes the same on-chip memory addresses used for single-chip mode, in addition to ad-
dressing capabilities for external peripheral and memory devices. The expansion bus is made up of
ports B, C, and F, and the R/W signal. In expanded operating mode, high order address bits are output
on the port B pins, low order address bits on the port F pins, and the data bus on port C. The R/W pin
controls the direction of data transfer on the port C bus.
Bootstrap mode allows special-purpose programs to be entered into internal RAM. The bootloader pro-
gram uses the serial communications interface (SCI) to read a program of up to 768 bytes into on-chip
RAM. After a four-character delay, or after receiving the character for address $037F ($047F for
MC68HC11KA2), control passes to the loaded program at $0080.
Special test mode is used primarily for factory testing.
2.2 On-Chip Memory
The M68HC11 CPU is capable of addressing a 64 Kbyte range. The INIT, INIT2, and CONFIG registers
control the existence and locations of the registers, RAM, EEPROM, and ROM in the physical 64 Kbyte
memory space. Addressing beyond the 64 Kbyte range is possible using a memory paging scheme in
expanded mode only.
The 128-byte register block originates at $0000 after reset and can be placed at any other 4 Kbyte
boundary ($x000) after reset by writing an appropriate value to the INIT register.
The 768-byte RAM (1024 bytes in the MC68HC11KA2) can be remapped to any 4 Kbyte boundary in
memory.
The RAM in the MC68HC11KA4 is divided into two sections of 128 bytes and 640 bytes. For the
MC68HC11KA4, 128 bytes of the RAM are mapped at $0000–$007F unless the registers are mapped
to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300
to $037F.
The RAM in the MC68HC11KA2 is divided into two sections of 128 bytes and 896 bytes. For the
MC68HC11KA2, 128 bytes of the RAM are mapped at $0000–$007F unless the registers are mapped
to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300
to $047F.
Remapping is accomplished by writing appropriate values into the two nibbles of the INIT register. Refer
to the register and RAM mapping examples following the MC68HC11KA4 and MC68HC11KA2 memory
maps.
The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the
memory map by the CONFIG register. EEPROM can be placed at any other 4 Kbyte boundary ($xD80)
by writing appropriate values to the INIT2 register.
The ROMAD and ROMON control bits in the CONFIG register control the position and presence of
ROM/EPROM in the memory map. In special test mode, the ROMON bit is forced to zero so that the
ROM/EPROM is removed from the memory map. In single-chip mode, the ROMAD bit is forced to one,
causing the ROM/EPROM to be enabled at $A000–$FFFF ($8000–$FFFF in the MC68HC11KA2). This
guarantees that there will be ROM/EPROM at the vector space.
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
11

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