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PDF M68AW512D Data sheet ( Hoja de datos )

Número de pieza M68AW512D
Descripción 8 Mbit 512K x16 3.0V Asynchronous SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M68AW512D Hoja de datos, Descripción, Manual

M68AW512D
8 Mbit (512K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY
s SUPPLY VOLTAGE: 2.7 to 3.6V
s 512K x 16 bits SRAM with OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIMES: 55, 70ns
s LOW STANDBY CURRENT
s LOW VCC DATA RETENTION: 1.5V
s TRI-STATE COMMON I/O
s AUTOMATIC POWER DOWN
Figure 1. Packages
BGA
TFBGA48 (ZB)
8 x 10 mm
November 2002
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M68AW512D pdf
Figure 4. Block Diagram
E1 Ex
E2
UB
LB
W
G
M68AW512D
A18
A8
DQ15
UB
DQ0
LB
ROW
DECODER
MEMORY
ARRAY
(8) I/O CIRCUITS
COLUMN
DECODER
(8)
(8)
UB
(8)
LB
A0 A7
AI05452
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec may affect
device reliability. Refer also to the STMicroelec-
tronics SURE Program and other relevant quality
documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
TA Ambient Operating Temperature
TSTG
Storage Temperature
VCC Supply Voltage
VIO (1)
Input or Output Voltage
PD Power Dissipation
Note: 1. Up to a maximum operating VCC of 3.6V only.
Value
–55 to 125
–65 to 150
–0.5 to 4.6
–0.5 to VCC +0.5
1
Unit
°C
°C
V
V
W
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M68AW512D arduino
M68AW512D
Write Mode
The M68AW512D, when Chip Select (E2) is High,
is in the Write Mode whenever the W and E1 are
Low. Either the Chip Enable Input (E1) or the Write
Enable input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
When E1 or W is Low, and UB or LB is Low, write
cycle begins on the W or E1 falling edge. When E1
and W are Low, and UB = LB = High, write cycle
begins on the first falling edge of UB or LB. There-
fore, address setup time is referenced to Write En-
able, Chip Enables and UB/LB as tAVWL, tAVEL and
tAVBL respectively, and is determined by the latter
occurring falling edge.
The Write cycle can be terminated by the earlier
rising edge of E1, W, UB and LB.
If the Output is enabled (E1 = Low, E2 = High, G =
Low, LB or UB = Low), then W will return the out-
puts to high impedance within tWLQZ of its falling
edge. Care must be taken to avoid bus contention
in this type of operation. Data input must be valid
for tDVWH before the rising edge of Write Enable,
or for tDVEH before the rising edge of E1 or for tD-
VBH before the rising edge of UB/LB, whichever
occurs first, and remain valid for tWHDX, tEHDX and
tBHDX respectively.
Figure 10. Write Enable Controlled, Write AC Waveforms
A0-A18
tAVEL
E1
tAVAV
VALID
tAVWH
tELWH
tWHAX
E2
W
DQ0-DQ15
UB, LB
tAVWL
tWLWH
tWLQZ
tBLBH
tWHDX
DATA INPUT
tDVWH
tWHQX
AI05982
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
11/18

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