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PDF M68AW064F Data sheet ( Hoja de datos )
| Número de pieza | M68AW064F | |
| Descripción | 1 Mbit 64K x16 3.0V Asynchronous SRAM | |
| Fabricantes | ST Microelectronics | |
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M68AW064F
1 Mbit (64K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY
s SUPPLY VOLTAGE: 2.7 to 3.6V
s 64K x 16 bits SRAM with OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIME: 55ns and
70ns
s LOW STANDBY CURRENT
s LOW VCC DATA RETENTION: 2.0V
s TRI-STATE COMMON I/O
s AUTOMATIC POWER DOWN
Figure 1. Packages
BGA
TFBGA48 (ZB)
6 x 8 solder balls
April 2003
1/18
1 page  
Figure 4. Block Diagram
W
E
UB
LB
G
M68AW064F
A15
A7
DQ15
UB
DQ0
LB
ROW
DECODER
MEMORY
ARRAY
VCC
VSS
(8) I/O CIRCUITS
COLUMN
DECODER
(8)
(8)
UB
(8)
LB
A0 A6
AI04875
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
Table 2. Absolute Maximum Ratings
Symbol
Parameter
IO (1)
Output Current
TA Ambient Operating Temperature
TSTG
Storage Temperature
VCC Supply Voltage
VIO (2)
Input or Output Voltage
PD Power Dissipation
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating VCC of 3.6V only.
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Value
20
–55 to 125
–65 to 150
–0.5 to 4.6
–0.5 to VCC +0.5
1
Unit
mA
°C
°C
V
V
W
5/18
5 Page 
M68AW064F
Write Mode
The M68AW064F is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)’s
falling edge. Therefore, address setup time is
referenced to Write Enable as tAVWL and to Chip
Enable as tAVEL and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low, LB or
UB = Low), then W will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for tDVWH
before the rising edge of Write Enable, or for tDVEH
before the rising edge of E, whichever occurs first,
and remain valid for tWHDX and tEHDX respectively.
Figure 10. Write Enable Controlled, Write AC Waveforms
A0-A15
E
W
DQ0-DQ15
UB, LB
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tBLWH
tWHDX
DATA INPUT
tDVWH
tWHQX
AI04878
11/18
11 Page | ||
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