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PDF M68AW031AM70NS6U Data sheet ( Hoja de datos )

Número de pieza M68AW031AM70NS6U
Descripción 256 Kbit (32K x8) 3.0V Asynchronous SRAM
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M68AW031A
256 Kbit (32K x8) 3.0V Asynchronous SRAM
FEATURES SUMMARY
s SUPPLY VOLTAGE: 2.7 to 3.6V
s 32K x 8 bits SRAM with OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIME: 70ns
s LOW STANDBY CURRENT
s LOW VCC DATA RETENTION: 1.5V
s TRI-STATE COMMON I/O
s AUTOMATIC POWER DOWN
Figure 1. Packages
SO28 (MS)
TSOP28 (N)
8 x 13.4 mm
TSOP28 (NS)
8 x 13.4 mm (Reverse)
October 2002
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M68AW031AM70NS6U pdf
Figure 6. Block Diagram
A14
A7
DQ7
DQ0
M68AW031A
ROW
DECODER
MEMORY
ARRAY
I/O CIRCUITS
COLUMN
DECODER
A0 A6
E
W
G
AI05919
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
Table 2. Absolute Maximum Ratings
Symbol
Parameter
IO (1)
Output Current
TA Ambient Operating Temperature
TSTG
Storage Temperature
VCC Supply Voltage
VIO (2)
Input or Output Voltage
PD Power Dissipation
Note: 1. One output at time not to exceed 1 second duration.
2. Up to a maximum operating VCC of 3.6V only.
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec periods may
affect device reliability. Refer also to the STMicro-
electronics SURE Program and other relevant
quality documents.
Value
20
–55 to 125
–65 to 150
–0.5 to 4.6
–0.5 to VCC +0.5
1
Unit
mA
°C
°C
V
V
W
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M68AW031AM70NS6U arduino
M68AW031A
Write Mode
The M68AW031A is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, write
cycle begins on the W (E)’s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, whichever occurs first, and remain valid
for tWHDX and tEHDX respectively.
Figure 12. Write Enable Controlled, Write AC Waveforms
A0-A14
E
W
DQ0-DQ7
tAVAV
VALID
tAVWH
tELWH
tWHAX
tAVWL
tWLWH
tWLQZ
DATA (1)
tWHDX
DATA INPUT
tDVWH
tWHQX
DATA (1)
AI05941
Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.
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