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PDF M37471M8 Data sheet ( Hoja de datos )

Número de pieza M37471M8
Descripción SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fabricantes Mitsubishi 
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MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7470/7471 group is a single-chip microcomputer designed
with CMOS silicon gate technology. It is housed in a 32-pin shrink
plastic molded DIP. The M37471M2-XXXSP/FP is a single-chip mi-
crocomputer designed with CMOS silicon gate technology. It is
housed in a 42-pin shrink plastic molded DIP or a 56-pin plastic
molded QFP.
These single-chip microcomputer are useful for business equip-
ment and other consumer applications.
In addition to its simple instruction set, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy
programming .
The differences between the M37471M2-XXXSP and the
M37471M2-XXXFP are the package outline and the power dissi-
pation ability (absolute maximum ratings).
The differences among M37470M2-XXXSP, M37470M4-XXXSP,
M37470M8-XXXSP, M37471M2-XXXSP/FP, M37471M4-XXXSP/
FP and M37471M8-XXXSP/FP are noted below.
Type name
M37470M2-XXXSP
M37471M2-XXXSP/FP
M37470M4-XXXSP
M37471M4-XXXSP/FP
M37470M8-XXXSP
M37471M8-XXXSP/FP
ROM size
4096 bytes
8192 bytes
16384 bytes
RAM size
128 bytes
192 bytes
384 bytes
I/O ports
26
36
26
36
26
36
FEATURES
qBasic machine-language instructions ...................................... 71
qMemory size
ROM ..................................................... 4096 bytes (M37471M2)
RAM ........................................................ 128 bytes (M37471M2)
qThe minimum instruction execution time
....................................... 0.5 µs (at 8 MHz oscillation frequency)
qPower source voltage
.............. 2.7 to 4.5 V (at 2.2VCC–2.0 MHz oscillation frequency)
............................... 4.5 to 5.5 V (at 8 MHz oscillation frequency)
qPower dissipation in normal mode
................................... 35 mW (at 8.0 MHz oscillation frequency)
qSubroutine nesting ...... 64 levels max. (M37470M2, M37471M2)
qInterrupt ................................................... 12 sources, 10 vectors
q8-bit timers .................................................................................. 4
qProgrammable I/O ports
(Ports P0, P1, P2, P4) ......................................... 22(7470 group)
28(7471 group)
qInput port (Port P3) ............................................... 4(7470 group)
(Ports P3, P5) ....................................... 8(7471 group)
qSerial I/O (8-bit) .......................................................................... 1
qA-D converter ............................... 8-bit, 4channels (7470 group)
8-bit, 8channels (7471 group)
PIN CONFIGURATION (TOP VIEW)
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/ T1
P12/ T0
P11
P10
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
XIN
XOUT
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
Outline 32P4B
P07
P06
P05
P04
P03
P02
P01
P00
P41
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
APPLICATION
Audio-visual equipment, VCR, Tuner,
Office automation equipment

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M37471M8 pdf
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5

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M37471M8 arduino
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts can be caused by 12 different sources consisting of five
external, six internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address speci-
fied in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt dis-
able flag is set.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT0 and INT1 can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
When the device is put into power-down state by the STP instruc-
tion or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT1 interrupt becomes a key on wake up inter-
rupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case, the port used for interrupt must have been set for the input
mode.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT1 interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt re-
quest nor INT1 interrupt request is generated.
The CNTR0/CNTR1 interrupts function in the same as INT0 and
INT1. The interrupt input pin can be specified for either CNTR0 or
CNTR1 pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection regis-
ter, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest pri-
ority. Figure 5 shows interrupts control.
Table 1. Interrupt vector address and priority
Interrupt source
Priority
RESET
1
INT0 interrupt
2
INT1 interrupt or key on wake up interrupt
3
CNTR0 interrupt or CNTR1 interrupt
4
Timer 1 interrupt
5
Timer 2 interrupt
6
Timer 3 interrupt
7
Timer 4 interrupt
8
Serial I/O interrupt
9
A-D conversion completion interrupt
10
BRK instruction interrupt
11
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
Remarks
Non-maskable
External interrupt (polarity programmable)
External interrupt (INT1 is polarity programmable)
External interrupt (polarity programmable)
Non-maskable software interrupt
11

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