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PDF M36WT864 Data sheet ( Hoja de datos )
| Número de pieza | M36WT864 | |
| Descripción | 64 Mbit 4Mb x16 / Multiple Bank / Burst Flash Memory and 8 Mbit 512K x16 SRAM / Multiple Memory Product | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M36WT864TF
M36WT864BF
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 8 Mbit (512K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDDF = 1.65V to 2.2V
– VDDS = VDDQF = 2.7V to 3.3V
– VPPF = 12V for Fast Program (optional)
s ACCESS TIME: 70, 85, 100ns
s LOW POWER CONSUMPTION
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36WT864TF: 8810h
– Bottom Device Code, M36WT864BF: 8811h
FLASH MEMORY
s PROGRAMMING TIME
– 8µs by Word typical for Fast Factory Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
s MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write operations
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
s 8 Mbit (512K x 16 bit)
s EQUAL CYCLE and ACCESS TIMES: 70ns
s LOW STANDBY CURRENT
s LOW VDDS DATA RETENTION: 1.5V
s TRI-STATE COMMON I/O
s AUTOMATIC POWER DOWN
Figure 1. Packages
FBGA
Stacked LFBGA96 (ZA)
8 x 14mm
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1 page  
M36WT864TF, M36WT864BF
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Flash DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. Flash DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. Flash Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. Flash Asynchronous Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Flash Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Flash Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. Flash Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 15. Flash Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. Flash Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 17. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 24. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 18. Flash Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. Flash Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19. SRAM Address Controlled, Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms . . . . . . . . . . . . 56
Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms . . . . . . . . . . . . . 57
Table 26. SRAM Read and Standby AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 22. SRAM Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 24. SRAM Write AC Waveforms, UB/LB Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. SRAM Low VDD Data Retention AC Waveforms, E1S Controlled. . . . . . . . . . . . . . . . . 61
Figure 26. SRAM Low VDD Data Retention AC Waveforms, E2S Controlled. . . . . . . . . . . . . . . . . 61
Table 28. SRAM Low VDD Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline
62
Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data 62
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
APPENDIX A. FLASH BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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5 Page 
M36WT864TF, M36WT864BF
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash mem-
ory and, E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
Figure 4. Functional Block Diagram
VDDF VDDQF VPPF
EF
GF
WF
RPF
WPF
LF
WAITF
KF
A19-A21
A0-A18
Flash Memory
64 Mbit (x16)
VDDS
VSSQF VSSF
DQ0-DQ15
E1S
E2S
GS
WS
UBS
LBS
SRAM
8 Mbit (x 16)
VSSS
AI06272
11/92
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M36WT864.PDF ] | |
Hoja de datos destacado
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| M36WT864 | 64 Mbit 4Mb x16 / Multiple Bank / Burst Flash Memory and 8 Mbit 512K x16 SRAM / Multiple Memory Product | ST Microelectronics |
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