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PDF M36W432BG Data sheet ( Hoja de datos )
| Número de pieza | M36W432BG | |
| Descripción | 32 Mbit 2Mb x16 / Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M36W432TG
M36W432BG
32 Mbit (2Mb x16, Boot Block) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
s MULTIPLE MEMORY PRODUCT
– 32 Mbit (2Mb x 16), Boot Block, Flash Memory
– 4 Mbit (256Kb x 16) SRAM Memory
s SUPPLY VOLTAGE
– VDDF = 2.7V to 3.3V
– VDDS = VDDQF = 2.7V to 3.3V
– VPPF = 12V for Fast Program (optional)
s ACCESS TIME: 70ns, 85ns
s LOW POWER CONSUMPTION
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36W432TG: 88BAh
– Bottom Device Code, M36W432BG: 88BBh
FLASH MEMORY
s MEMORY BLOCKS
– Parameter Blocks (Top or Bottom Location)
– Main Blocks
s PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
s AUTOMATIC STANDBY MODE
s PROGRAM and ERASE SUSPEND
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s COMMON FLASH INTERFACE
s SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device identifier
SRAM
s 4 Mbit (256Kb x 16)
s ACCESS TIME: 70ns
s LOW VDDS DATA RETENTION: 1.5V
s POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
Figure 1. Package
FBGA
Stacked LFBGA66 (ZA)
12 x 8 mm
November 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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1 page  
M36W432TG, M36W432BG
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 30. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 31. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. Flash Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 58
Figure 29. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 31. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. 63
Table 34. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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M36W432TG, M36W432BG
Table 2. Main Operation Modes
Operation
Mode
EF GF WF RPF WPF
VPPF
E1S E2S GS WS UBS LBS DQ15-DQ8 DQ7-DQ0
Read
VIL VIL VIH VIH X Don’t care
SRAM must be disabled
Data Output
Write
VIL VIH VIL VIH
X
VDDF or
VPPFH
SRAM must be disabled
Data Input
Block
Locking
VIL X X VIH VIL Don’t care
SRAM must be disabled
X
Standby VIH X X VIH X Don’t care Any SRAM mode is allowed
Hi-Z
Reset
X X X VIL X Don’t care Any SRAM mode is allowed
Hi-Z
Output
Disable
VIL VIH VIH VIH X Don’t care
Any SRAM mode is allowed
Hi-Z
Read
Flash must be disabled
VIL VIH VIL VIH VIL VIL Data out Word Read
Read
Flash must be disabled
VIL VIH VIL VIH VIL VIH Data out
Hi-Z
Read
Flash must be disabled
VIL VIH VIL VIH VIH VIL
Hi-Z Data out
Write
Flash must be disabled
VIL VIH X VIL VIL VIL Data in Word Write
Write
Flash must be disabled
VIL VIH X VIL VIH VIL
Data in
Hi-Z
Write
Flash must be disabled
VIL VIH X VIL VIL VIH
Hi-Z
Data in
Standby/
Power
Down
Any Flash mode is allowable
VIH VIL X X X
X
X X X X VIH VIH
Hi-Z
Hi-Z
Data
Retention
Any Flash mode is allowable
VIH VIL X X X
X
X X X X VIH VIH
Hi-Z
Hi-Z
Output
Disable
Any Flash mode is allowable
VIL VIH VIH VIH VIL VIL
Hi-Z
Output
Disable
Any Flash mode is allowable
VIL VIH VIH VIH VIL VIH
Hi-Z
Output
Disable
Any Flash mode is allowable
VIL VIH VIH VIH VIH VIL
Hi-Z
Note: 1. X = Don’t Care = VIL or VIH, VPPFH = 12V ± 5%.
2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
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