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PDF M36DR432B Data sheet ( Hoja de datos )

Número de pieza M36DR432B
Descripción 32 Mbit 2Mb x16 / Dual Bank / Page Flash Memory and 4 Mbit 256K x16 SRAM / Multiple Memory Product
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M36DR432A
M36DR432B
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and 4 Mbit (256K x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDDF = VDDS =1.65V to 2.2V
– VPPF = 12V for Fast Program (optional)
s ACCESS TIME: 100,120ns
s LOW POWER CONSUMPTION
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36DR432A: 00A0h
– Bottom Device Code, M36DR432B: 00A1h
FLASH MEMORY
s 32 Mbit (2Mb x16) BOOT BLOCK
– Parameter Blocks (Top or Bottom Location)
s PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
s ASYNCRONOUS PAGE MODE READ
– Page width: 4 Word
– Page Mode Access Time: 35ns
s DUAL BANK OPERATION
– Read within one Bank while Program or
Erase within the other
– No Delay between Read and Write
Operations
s BLOCK PROTECTION ON ALL BLOCKS
– WPF for Block Locking
s COMMON FLASH INTERFACE
– 64 bit Security Code
SRAM
s 4 Mbit (256K x 16 bit)
s LOW VDDS DATA RETENTION: 1V
s POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
Figure 1. Packages
FBGA
Stacked LFBGA66 (ZA)
8 x 8 ball array
November 2001
1/46

1 page




M36DR432B pdf
M36DR432A, M36DR432B
SIGNAL DESCRIPTIONS
See Figure 2 and Table 1.
Address Inputs (A0-A17). Addresses A0 to A17
are common inputs for the Flash chip and the
SRAM chip. The address inputs for the Flash
memory are latched during a write operation on
the falling edge of the Flash Chip Enable (EF) or
Write Enable (WF), while address inputs for the
SRAM array are latched during a write operation
on the falling edge of the SRAM Chip Enable lines
(E1S or E2S) or Write Enable (WS).
Address Inputs (A18-A20). Address A18 to A20
are address inputs for the Flash chip. They are
latched during a write operation on the falling edge
of Flash Chip Enable (EF) or Write Enable (WF).
Data Input/Outputs (DQ0-DQ15). The input is
data to be programmed in the Flash or SRAM
memory array or a command to be written to the
C.I. of the Flash chip. Both are latched on the ris-
ing edge of Flash Chip Enable (EF) or Write En-
able (WF) and, SRAM Chip Enable lines (E1S or
E2S) or Write Enable (WS). The output is data
from the Flash memory or SRAM array, the Elec-
tronic Signature Manufacturer or Device codes or
the Status register Data Polling bit DQ7, the Tog-
gle Bits DQ6 and DQ2, the Error bit DQ5 or the
Erase Timer bit DQ3. Outputs are valid when
Flash Chip Enable (EF) and Output Enable (GF) or
SRAM Chip Enable lines (E1S or E2S) and Output
Enable (GS) are active. The output is high imped-
ance when the both the Flash chip and the SRAM
chip are deselected or the outputs are disabled
and when Reset (RPF) is at a VIL.
Flash Chip Enable (EF). The Chip Enable input
for Flash activates the memory control logic, input
buffers, decoders and sense amplifiers. EF at VIH
deselects the memory and reduces the power con-
sumption to the standby level and output do Hi-Z.
EF can also be used to control writing to the com-
mand register and to the Flash memory array,
while WF remains at VIL. It is not allowed to set EF
at VIL, E1S at VIL and E2S at VIH at the same time.
Flash Write Enable (WF). The Write Enable in-
put controls writing to the Command Register of
the Flash chip and Address/Data latches. Data are
latched on the rising edge of WF.
Flash Output Enable (GF). The Output Enable
gates the outputs through the data buffers during
a read operation of the Flash chip. When GF and
WF are High the outputs are High impedance.
Flash Reset/Power Down Input (RPF). The RPF
input provides hardware reset of the memory
(without affecting the Configuration Register sta-
tus), and/or Power Down functions, depending on
the Configuration Register status. Reset/Power
Down of the memory is achieved by pulling RPF to
VIL for at least tPLPH. When the reset pulse is giv-
en, if the memory is in Read, Erase Suspend Read
or Standby, it will output new valid data in tPHQ7V1
after the rising edge of RPF. If the memory is in
Erase or Program modes, the operation will be
aborted and the reset recovery will take a maxi-
mum of tPLQ7V. The memory will recover from
Power Down (when enabled) in tPHQ7V2 after the
rising edge of RPF. See Tables 1, 26 and Figure
11.
Flash Write Protect (WPF). Write Protect is an
input to protect or unprotect the two lockable pa-
rameter blocks of the Flash memory. When WPF
is at VIL, the lockable blocks are protected. Pro-
gram or erase operations are not achievable.
When WPF is at VIH, the lockable blocks are un-
protected and they can be programmed or erased
(refer to Table 17).
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs for SRAM activate the memory control
logic, input buffers and decoders. E1S at VIH or
E2S at VIL deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at VIL. It
is not allowed to set EF at VIL, E1S at VIL and E2S
at VIH at the same time.
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM chip. GS is active
low.
SRAM Upper Byte Enable (UBS). Enable the
upper bytes for SRAM (DQ8-DQ15). UBS is active
low.
SRAM Lower Byte Enable (LBS). Enable the
lower bytes for SRAM (DQ0-DQ7). LBS is active
low.
VDDF Supply Voltage (1.65V to 2.2V). Flash memo-
ry power supply for all operations (Read, Program and
Erase).
VPPF Programming Voltage (11.4V to 12.6V).
Used to provide high voltage for fast factory pro-
gramming. High voltage on VPPF pin is required to
use the Double Word Program instruction. It is
also possible to perform word program or erase in-
structions with VPPF pin grounded.
VDDS Supply Voltage (1.65V to 2.2V). SRAM
power supply for all operations (Read, Program).
VSSF and VSSS Ground. VSSF and VSSS are the
reference for all voltage measurements respec-
tively in the Flash and SRAM chips.
5/46

5 Page





M36DR432B arduino
M36DR432A, M36DR432B
INSTRUCTIONS AND COMMANDS
Seventeen instructions are defined (see Table
15), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits can be read at any time, dur-
ing programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 15). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro-
gram data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
Table 13. Commands
Hex Code
Command
00h Bypass Reset
10h Bank Erase Confirm
20h Unlock Bypass
30h Block Erase Resume/Confirm
40h Double Word Program
Block Protect, or
60h
Block Unprotect, or
Block Lock, or
Write Configuration Register
80h Set-up Erase
Read Electronic Signature, or
90h Block Protection Status, or
Configuration Register Status
98h CFI Query
A0h Program
B0h Erase Suspend
F0h Read Array/Reset
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query mode is entered writing 98h at ad-
dress 55h. The CFI data structure gives informa-
tion on the device, such as the sectorization, the
command set and some electrical specifications.
Table 18, 19, 20 and 21 show the addresses used
to retrieve each data. The CFI data structure con-
tains also a security area; in this section, a 64 bit
unique security number is written, starting at ad-
dress 80h. This area can be accessed only in read
mode by the final user and there are no ways of
changing the code after it has been written by ST.
Write a read instruction (RD) to return to Read
mode.
Auto Select (AS) Instruction. This instruction uses
two Coded Cycles followed by one write cycle giv-
ing the command 90h to address 555h for com-
mand set-up. A subsequent read will output the
Manufacturer or the Device Code (Electronic Sig-
nature), the Block Protection status or the Config-
uration Register status depending on the levels of
A0 and A1 (see Table 10, 11 and 12). A7-A2 must
be at VIL, while other address input are ignored.
11/46

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