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PDF M36DR432AD Data sheet ( Hoja de datos )

Número de pieza M36DR432AD
Descripción 32 Mbit 2Mb x16 / Dual Bank / Page Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M36DR432AD Hoja de datos, Descripción, Manual

M36DR432AD
M36DR432BD
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
s Multiple Memory Product
– 1 bank of 32 Mbit (2Mb x16) Flash Memory
– 1 bank of 4 Mbit (256Kb x16) SRAM
s SUPPLY VOLTAGE
– VDDF = VDDS =1.65V to 2.2V
– VPPF = 12V for Fast Program (optional)
s ACCESS TIMES: 85ns, 100ns, 120ns
s LOW POWER CONSUMPTION
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code, M36DR432AD: 00A0h
– Bottom Device Code, M36DR432BD: 00A1h
FLASH MEMORY
s MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit, 28 Mbit
– Parameter Blocks (Top or Bottom location)
s PROGRAMMING TIME
– 10µs by Word typical
– Double Word Program Option
s ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 Words
– Page Access: 35ns
– Random Access: 85ns, 100ns, 120ns
s DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
s COMMON FLASH INTERFACE (CFI)
– 64 bit Unique Device Identifier
– 64 bit User Programmable OTP Cells
Figure 1. Package
FBGA
Stacked LFBGA66 (ZA)
12 x8mm
s ERASE SUSPEND and RESUME MODES
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
SRAM
s 4 Mbit (256Kb x16)
s LOW VDDS DATA RETENTION: 1.0V
s POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
February 2003
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1 page




M36DR432AD pdf
M36DR432AD, M36DR432BD
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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M36DR432AD arduino
M36DR432AD, M36DR432BD
Table 2. Main Operation Modes
Operation Mode
EF GF WF RPF WPF ES GS WS UBS, LBS(1) DQ15-DQ0
Read
VIL VIL VIH VIH
VIH
SRAM must be disabled
Data Output
Page Read
VIL VIL VIH VIH
VIH
SRAM must be disabled
Data Output
Write
VIL VIH VIL VIH
VIH
SRAM must be disabled
Data Input
Standby
VIH X X VIH VIH
Any SRAM mode is allowed
Hi-Z
Reset/
Power-Down
X X X VIL VIH
Any SRAM mode is allowed
Hi-Z
Output Disable
VIL VIH VIH VIH
VIH
Any SRAM mode is allowed
Hi-Z
Read
Flash must be disabled
VIL VIL VIH
VIL
Data out
Word Read
Write
Flash must be disabled
VIL VIH VIL
VIL
Data in Word
Write
Standby/Power
Down
Any Flash mode is allowable
VIH X X
X XX
X
VIH
Hi-Z
Hi-Z
Data Retention
Any Flash mode is allowable
VIH X X
X XX
X
VIH
Hi-Z
Hi-Z
Output Disable
Any Flash mode is allowable
VIL VIH VIH
X
Note: 1. X = Don’t care (VIL or VIH).
2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
Hi-Z
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