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PDF M366S1723FTS-C7A Data sheet ( Hoja de datos )

Número de pieza M366S1723FTS-C7A
Descripción SDRAM Unbuffered Module
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! M366S1723FTS-C7A Hoja de datos, Descripción, Manual

64MB, 128MB, 256MB Unbuffered DIMM
SDRAM
SDRAM Unbuffered Module
168pin Unbuffered Module based on 128Mb F-die
62/72-bit Non ECC/ECC
Revision 1.3
May 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 May 2004

1 page




M366S1723FTS-C7A pdf
64MB, 128MB, 256MB Unbuffered DIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
CLK
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
CS Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11
Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
REGE
Register enable
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data input/output
Check bit
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power and ground for the input buffers and the core logic.
Rev. 1.3 May 2004

5 Page





M366S1723FTS-C7A arduino
64MB, 128MB, 256MB Unbuffered DIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1.0 * # of component
50
Unit
V
V
°C
W
mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Symbol
VDD
VIH
VIL
VOH
VOL
ILI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ Max Unit
3.3 3.6
V
3.0 VDDQ+0.3
V
0 0.8 V
- -V
- 0.4 V
- 10 uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter
Input capacitance (A0 ~ A11)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE)
Input capacitance (CLK)
Input capacitance (CS)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
Sym-
bol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
M366S0924FTS
Min Max
15 25
15 25
15 25
10 13
10 15
8 10
9 12
M366S1723FTS(U)
Min Max
25 45
25 45
25 45
15 21
15 25
8 12
9 12
M366S3323FTS(U)
Min Max
45 85
45 85
25 45
15 21
15 25
10 15
13 18
Unit
pF
pF
pF
pF
pF
pF
pF
Pin
Input capacitance (A0 ~ A11)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE)
Input capacitance (CLK)
Input capacitance (CS)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63
Sym-
bol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
M374S1723FTS(U)
Min Max
28 50
28 50
28 50
18 25
18 30
8 10
9 12
M374S3323FTS(U)
Min Max
50 95
50 95
28 50
18 25
18 30
13 20
13 18
Unit
pF
pF
pF
pF
pF
pF
pF
Rev. 1.3 May 2004

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