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PDF M34D32 Data sheet ( Hoja de datos )
| Número de pieza | M34D32 | |
| Descripción | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M34D64
M34D32
64/32 Kbit Serial I²C Bus EEPROM
With Hardware Write Control on Top Quarter of Memory
PRELIMINARY DATA
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 4.5V to 5.5V for M34Dxx
– 2.5V to 5.5V for M34Dxx-W
– 1.8V to 3.6V for M34Dxx-R
s Hardware Write Control of the top quarter of
memory
s BYTE and PAGE WRITE (up to 32 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s More than 1 Million Erase/Write Cycles
s More than 40 Year Data Retention
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
DESCRIPTION
These electrically erasable programmable
memory (EEPROM) devices are fabricated with
STMicroelectronics’ High Endurance, CMOS
technology. This guarantees an endurance
typically well above one million Erase/Write
cycles, with a data retention of 40 years. The
memories are organized as 8192x8 bits (M34D64)
and 4096x8 bits (M34D32), and operate down to
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC Write Control
VCC
VSS
Supply Voltage
Ground
3
E0-E2
SCL
WC
M34D64
M34D32
SDA
VSS
AI02850
May 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/15
1 page  
Table 3. Device Select Code 1
Device Type Identifier
b7 b6 b5
Device Select Code
1
0
Note: 1. The most significant bit, b7, is sent first.
1
b4
0
M34D64, M34D32
Chip Enable
b3 b2 b1
E2 E1 E0
RW
b0
RW
transition, and the data must change only when
the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9th bit time. If the memory does not
match the Device Select Code, it deselects itself
from the bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 to b13 are Don’t Care on the M34D64 series.
b15 to b12 are Don’t Care on the M34D32 series.
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
significant Byte (Table 5). Bits b15 to b0 form the
address of the byte in memory. Bits b15 to b13 are
treated as a Don’t Care bit on the M34D64
memory. Bits b15 to b12 are treated as Don’t Care
bits on the M34D32 memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory
responds to each address byte with an
acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the contents of the top quarter of
the memory.
Table 6. Operating Modes
Mode
RW bit
Current Address Read
1
Random Address Read
0
1
Sequential Read
1
Byte Write
0
Page Write
Note: 1. X = VIH or VIL.
0
WC 1
X
X
X
X
VIL
VIL
Bytes
1
1
≥1
1
≤ 32
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
5/15
5 Page 
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
SDA IN
tCHDX
tCLDX
START
CONDITION
SDA
SDA
INPUT CHANGE
SCL
SDA OUT
tCLQV
DATA VALID
tCLQX
DATA OUTPUT
M34D64, M34D32
tCHDH
tDHDL
STOP &
BUS FREE
SCL
SDA IN
tCHDH
STOP
CONDITION
tW
WRITE CYCLE
tCHDX
START
CONDITION
AI00795B
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M34D32.PDF ] | |
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