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PDF M34C00DW Data sheet ( Hoja de datos )
| Número de pieza | M34C00DW | |
| Descripción | 3 x 128 bit Serial IC Bus EEPROM For ee-Tags | |
| Fabricantes | ST Microelectronics | |
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M34C00
3 x 128 bit Serial I²C Bus EEPROM
For ee-Tags
PRELIMINARY DATA
s Two-Wire I2C Serial Interface
Supports 400 kHz Protocol
s 2.5 V to 5.5 V Single Supply Voltage
s 384-bit EEPROM divided in three areas:
– 128 bits of non-erasable memory
– 128 bits of standard EEPROM
– 128 bits that can be permanently Write-
protected (to behave as ROM)
s Self-Timed Program Cycle
s Enhanced ESD/Latch-Up Protection
s More than 1 Million Erase/Write Cycles
s More than 40 Year Data Retention
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
The M34C00 is a 384-bit serial EEPROM. The
bottom third of the memory area (from location 00h
to 0Fh) can be Write-protected using a specially
designed software Write-protection mechanism.
By sending the device a specific sequence, the
first 128 bits of the memory become permanently
Write-protected. Care must be taken when using
this sequence as its effect cannot be reversed.
The top third of the memory area (from location
20h to 2Fh) is already configured to give the
functional equivalence of a non-erasable memory.
That is, it is initialized to all 1s (FFh), and the user
is able to reset any number of those 1s to 0; but
there is no mechanism for the user to set a 0 back
to a 1.
The M34C00 is a 384-bit electrically erasable
programmable memory (EEPROM), organized as
48 x 8 bits.
Figure 1. Logic Diagram
VCC
SCL M34C00
SDA
Table 1. Signal Names
SDA
Serial Data
SCL
Serial Clock
VCC
Supply Voltage
VSS Ground
VSS
AI03394
August 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/15
1 page  
Figure 5. Memory Partitioning
M34C00
Array 2
Array 1
Array 0
EPROM
Array
Standard
Array
Standard
Array
2Fh
20h
1Fh
10h
0Fh
00h
Default EEPROM memory area
state before write access
to the Protection Register
Array 2
Array 1
Array 0
EPROM
Array
Standard
Array
Write
Protected
Array
2Fh
20h
1Fh
10h
0Fh
00h
State of the EEPROM memory
area after write access
to the Protection Register
AI03396
address the Invalid array, and immediately
deselects itself.
The Write-protectable array consists of 16 bytes of
EEPROM, which can be used as normal EEPROM
until this array is set in its Write-protected mode.
Once Write-protected, this array becomes
functionally equivalent to a Read-Only Memory
(ROM), and cannot be modified further. The
procedure to set this array in its Write-protected
mode is described later.
Array-2 also consists of 16 bytes of EEPROM, but
configured to give the functional equivalence of
non-erasable memory. That is, it is initialized to
contain all 1s (FFh), with the user able to reset any
1 to a 0, but unable to set any 0 to a 1. One
application envisaged for this array is as a non-
resettable 128-token array.
WRITE AND READ OPERATIONS
Write Operations
Following a Start condition the bus master sends
a Device Select code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
6, and waits for an address byte. The device
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the
addressed location is in the Write-protected area,
the device replies with NoAck, and the location is
not modified. If, instead, the addressed location is
not in a Write-protected area, the device replies
with Ack. The bus master terminates the transfer
by generating a Stop condition, as shown in Figure
6.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table 6,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the bus
master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select code (the first byte
of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
5/15
5 Page 
Table 8. Ordering Information Scheme
Example:
M34C00 – W MN 6
T
Operating Voltage
W 2.5 V to 5.5 V
Package
MN SO8 (150 mil width)
DW TSSOP8 (169 mil width)
M34C00
Option
T Tape and Reel Packing
Temperature Range
6 –40 °C to 85 °C
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh), and the
Protection Register set at all 0s (00h).
The notation used for the device number is as
shown in Table 8. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
11/15
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